Syntax of gfx90a Instructions¶
Introduction¶
This document describes the syntax of gfx90a instructions.
Notation¶
Notation used in this document is explained here.
Overview¶
An overview of generic syntax and other features of AMDGPU instructions may be found in this document.
Instructions¶
DS¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS ————————————————————————————————————————————————————————————————————————————————————————————————— ds_add_f32 vaddr, vdata offset gds ds_add_f64 vaddr, vdata offset gds ds_add_rtn_f32 vdst, vaddr, vdata offset gds ds_add_rtn_f64 vdst, vaddr, vdata offset gds ds_add_rtn_u32 vdst, vaddr, vdata offset gds ds_add_rtn_u64 vdst, vaddr, vdata offset gds ds_add_u32 vaddr, vdata offset gds ds_add_u64 vaddr, vdata offset gds ds_and_b32 vaddr, vdata offset gds ds_and_b64 vaddr, vdata offset gds ds_and_rtn_b32 vdst, vaddr, vdata offset gds ds_and_rtn_b64 vdst, vaddr, vdata offset gds ds_append vdst offset gds ds_bpermute_b32 vdst, vaddr, vdata offset ds_cmpst_b32 vaddr, vdata0, vdata1 offset gds ds_cmpst_b64 vaddr, vdata0, vdata1 offset gds ds_cmpst_f32 vaddr, vdata0, vdata1 offset gds ds_cmpst_f64 vaddr, vdata0, vdata1 offset gds ds_cmpst_rtn_b32 vdst, vaddr, vdata0, vdata1 offset gds ds_cmpst_rtn_b64 vdst, vaddr, vdata0, vdata1 offset gds ds_cmpst_rtn_f32 vdst, vaddr, vdata0, vdata1 offset gds ds_cmpst_rtn_f64 vdst, vaddr, vdata0, vdata1 offset gds ds_condxchg32_rtn_b64 vdst, vaddr, vdata offset gds ds_consume vdst offset gds ds_dec_rtn_u32 vdst, vaddr, vdata offset gds ds_dec_rtn_u64 vdst, vaddr, vdata offset gds ds_dec_u32 vaddr, vdata offset gds ds_dec_u64 vaddr, vdata offset gds ds_gws_barrier vdata offset gds ds_gws_init vdata offset gds ds_gws_sema_br vdata offset gds ds_gws_sema_p offset gds ds_gws_sema_release_all offset gds ds_gws_sema_v offset gds ds_inc_rtn_u32 vdst, vaddr, vdata offset gds ds_inc_rtn_u64 vdst, vaddr, vdata offset gds ds_inc_u32 vaddr, vdata offset gds ds_inc_u64 vaddr, vdata offset gds ds_max_f32 vaddr, vdata offset gds ds_max_f64 vaddr, vdata offset gds ds_max_i32 vaddr, vdata offset gds ds_max_i64 vaddr, vdata offset gds ds_max_rtn_f32 vdst, vaddr, vdata offset gds ds_max_rtn_f64 vdst, vaddr, vdata offset gds ds_max_rtn_i32 vdst, vaddr, vdata offset gds ds_max_rtn_i64 vdst, vaddr, vdata offset gds ds_max_rtn_u32 vdst, vaddr, vdata offset gds ds_max_rtn_u64 vdst, vaddr, vdata offset gds ds_max_u32 vaddr, vdata offset gds ds_max_u64 vaddr, vdata offset gds ds_min_f32 vaddr, vdata offset gds ds_min_f64 vaddr, vdata offset gds ds_min_i32 vaddr, vdata offset gds ds_min_i64 vaddr, vdata offset gds ds_min_rtn_f32 vdst, vaddr, vdata offset gds ds_min_rtn_f64 vdst, vaddr, vdata offset gds ds_min_rtn_i32 vdst, vaddr, vdata offset gds ds_min_rtn_i64 vdst, vaddr, vdata offset gds ds_min_rtn_u32 vdst, vaddr, vdata offset gds ds_min_rtn_u64 vdst, vaddr, vdata offset gds ds_min_u32 vaddr, vdata offset gds ds_min_u64 vaddr, vdata offset gds ds_mskor_b32 vaddr, vdata0, vdata1 offset gds ds_mskor_b64 vaddr, vdata0, vdata1 offset gds ds_mskor_rtn_b32 vdst, vaddr, vdata0, vdata1 offset gds ds_mskor_rtn_b64 vdst, vaddr, vdata0, vdata1 offset gds ds_nop ds_or_b32 vaddr, vdata offset gds ds_or_b64 vaddr, vdata offset gds ds_or_rtn_b32 vdst, vaddr, vdata offset gds ds_or_rtn_b64 vdst, vaddr, vdata offset gds ds_permute_b32 vdst, vaddr, vdata offset ds_read2_b32 vdst:b32x2, vaddr offset0 offset1 gds ds_read2_b64 vdst:b64x2, vaddr offset0 offset1 gds ds_read2st64_b32 vdst:b32x2, vaddr offset0 offset1 gds ds_read2st64_b64 vdst:b64x2, vaddr offset0 offset1 gds ds_read_addtid_b32 vdst offset gds ds_read_b128 vdst, vaddr offset gds ds_read_b32 vdst, vaddr offset gds ds_read_b64 vdst, vaddr offset gds ds_read_b96 vdst, vaddr offset gds ds_read_i16 vdst, vaddr offset gds ds_read_i8 vdst, vaddr offset gds ds_read_i8_d16 vdst, vaddr offset gds ds_read_i8_d16_hi vdst, vaddr offset gds ds_read_u16 vdst, vaddr offset gds ds_read_u16_d16 vdst, vaddr offset gds ds_read_u16_d16_hi vdst, vaddr offset gds ds_read_u8 vdst, vaddr offset gds ds_read_u8_d16 vdst, vaddr offset gds ds_read_u8_d16_hi vdst, vaddr offset gds ds_rsub_rtn_u32 vdst, vaddr, vdata offset gds ds_rsub_rtn_u64 vdst, vaddr, vdata offset gds ds_rsub_u32 vaddr, vdata offset gds ds_rsub_u64 vaddr, vdata offset gds ds_sub_rtn_u32 vdst, vaddr, vdata offset gds ds_sub_rtn_u64 vdst, vaddr, vdata offset gds ds_sub_u32 vaddr, vdata offset gds ds_sub_u64 vaddr, vdata offset gds ds_swizzle_b32 vdst, vaddr pattern gds ds_wrap_rtn_b32 vdst, vaddr, vdata0, vdata1 offset gds ds_write2_b32 vaddr, vdata0, vdata1 offset0 offset1 gds ds_write2_b64 vaddr, vdata0, vdata1 offset0 offset1 gds ds_write2st64_b32 vaddr, vdata0, vdata1 offset0 offset1 gds ds_write2st64_b64 vaddr, vdata0, vdata1 offset0 offset1 gds ds_write_addtid_b32 vdata offset gds ds_write_b128 vaddr, vdata offset gds ds_write_b16 vaddr, vdata offset gds ds_write_b16_d16_hi vaddr, vdata offset gds ds_write_b32 vaddr, vdata offset gds ds_write_b64 vaddr, vdata offset gds ds_write_b8 vaddr, vdata offset gds ds_write_b8_d16_hi vaddr, vdata offset gds ds_write_b96 vaddr, vdata offset gds ds_wrxchg2_rtn_b32 vdst:b32x2, vaddr, vdata0, vdata1 offset0 offset1 gds ds_wrxchg2_rtn_b64 vdst:b64x2, vaddr, vdata0, vdata1 offset0 offset1 gds ds_wrxchg2st64_rtn_b32 vdst:b32x2, vaddr, vdata0, vdata1 offset0 offset1 gds ds_wrxchg2st64_rtn_b64 vdst:b64x2, vaddr, vdata0, vdata1 offset0 offset1 gds ds_wrxchg_rtn_b32 vdst, vaddr, vdata offset gds ds_wrxchg_rtn_b64 vdst, vaddr, vdata offset gds ds_xor_b32 vaddr, vdata offset gds ds_xor_b64 vaddr, vdata offset gds ds_xor_rtn_b32 vdst, vaddr, vdata offset gds ds_xor_rtn_b64 vdst, vaddr, vdata offset gds
FLAT¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS ———————————————————————————————————————————————————————————————————————————————————————————————————— flat_atomic_add vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_add_f64 vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_add_x2 vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_and vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_and_x2 vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_cmpswap vdst:opt, vaddr, vdata:b32x2 offset12 glc slc flat_atomic_cmpswap_x2 vdst:opt, vaddr, vdata:b64x2 offset12 glc slc flat_atomic_dec vdst:opt:u32, vaddr, vdata:u32 offset12 glc slc flat_atomic_dec_x2 vdst:opt:u64, vaddr, vdata:u64 offset12 glc slc flat_atomic_inc vdst:opt:u32, vaddr, vdata:u32 offset12 glc slc flat_atomic_inc_x2 vdst:opt:u64, vaddr, vdata:u64 offset12 glc slc flat_atomic_max_f64 vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_min_f64 vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_or vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_or_x2 vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_smax vdst:opt:i32, vaddr, vdata:i32 offset12 glc slc flat_atomic_smax_x2 vdst:opt:i64, vaddr, vdata:i64 offset12 glc slc flat_atomic_smin vdst:opt:i32, vaddr, vdata:i32 offset12 glc slc flat_atomic_smin_x2 vdst:opt:i64, vaddr, vdata:i64 offset12 glc slc flat_atomic_sub vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_sub_x2 vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_swap vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_swap_x2 vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_umax vdst:opt:u32, vaddr, vdata:u32 offset12 glc slc flat_atomic_umax_x2 vdst:opt:u64, vaddr, vdata:u64 offset12 glc slc flat_atomic_umin vdst:opt:u32, vaddr, vdata:u32 offset12 glc slc flat_atomic_umin_x2 vdst:opt:u64, vaddr, vdata:u64 offset12 glc slc flat_atomic_xor vdst:opt, vaddr, vdata offset12 glc slc flat_atomic_xor_x2 vdst:opt, vaddr, vdata offset12 glc slc flat_load_dword vdst, vaddr offset12 glc slc flat_load_dwordx2 vdst, vaddr offset12 glc slc flat_load_dwordx3 vdst, vaddr offset12 glc slc flat_load_dwordx4 vdst, vaddr offset12 glc slc flat_load_sbyte vdst, vaddr offset12 glc slc flat_load_sbyte_d16 vdst, vaddr offset12 glc slc flat_load_sbyte_d16_hi vdst, vaddr offset12 glc slc flat_load_short_d16 vdst, vaddr offset12 glc slc flat_load_short_d16_hi vdst, vaddr offset12 glc slc flat_load_sshort vdst, vaddr offset12 glc slc flat_load_ubyte vdst, vaddr offset12 glc slc flat_load_ubyte_d16 vdst, vaddr offset12 glc slc flat_load_ubyte_d16_hi vdst, vaddr offset12 glc slc flat_load_ushort vdst, vaddr offset12 glc slc flat_store_byte vaddr, vdata offset12 glc slc flat_store_byte_d16_hi vaddr, vdata offset12 glc slc flat_store_dword vaddr, vdata offset12 glc slc flat_store_dwordx2 vaddr, vdata offset12 glc slc flat_store_dwordx3 vaddr, vdata offset12 glc slc flat_store_dwordx4 vaddr, vdata offset12 glc slc flat_store_short vaddr, vdata offset12 glc slc flat_store_short_d16_hi vaddr, vdata offset12 glc slc global_atomic_add vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_add_f32 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_add_f64 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_add_x2 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_and vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_and_x2 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_cmpswap vdst:opt, vaddr, vdata:b32x2, saddr offset13s glc slc global_atomic_cmpswap_x2 vdst:opt, vaddr, vdata:b64x2, saddr offset13s glc slc global_atomic_dec vdst:opt:u32, vaddr, vdata:u32, saddr offset13s glc slc global_atomic_dec_x2 vdst:opt:u64, vaddr, vdata:u64, saddr offset13s glc slc global_atomic_inc vdst:opt:u32, vaddr, vdata:u32, saddr offset13s glc slc global_atomic_inc_x2 vdst:opt:u64, vaddr, vdata:u64, saddr offset13s glc slc global_atomic_max_f64 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_min_f64 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_or vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_or_x2 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_pk_add_f16 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_smax vdst:opt:i32, vaddr, vdata:i32, saddr offset13s glc slc global_atomic_smax_x2 vdst:opt:i64, vaddr, vdata:i64, saddr offset13s glc slc global_atomic_smin vdst:opt:i32, vaddr, vdata:i32, saddr offset13s glc slc global_atomic_smin_x2 vdst:opt:i64, vaddr, vdata:i64, saddr offset13s glc slc global_atomic_sub vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_sub_x2 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_swap vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_swap_x2 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_umax vdst:opt:u32, vaddr, vdata:u32, saddr offset13s glc slc global_atomic_umax_x2 vdst:opt:u64, vaddr, vdata:u64, saddr offset13s glc slc global_atomic_umin vdst:opt:u32, vaddr, vdata:u32, saddr offset13s glc slc global_atomic_umin_x2 vdst:opt:u64, vaddr, vdata:u64, saddr offset13s glc slc global_atomic_xor vdst:opt, vaddr, vdata, saddr offset13s glc slc global_atomic_xor_x2 vdst:opt, vaddr, vdata, saddr offset13s glc slc global_load_dword vdst:opt, vaddr, saddr offset13s glc slc lds global_load_dwordx2 vdst, vaddr, saddr offset13s glc slc global_load_dwordx3 vdst, vaddr, saddr offset13s glc slc global_load_dwordx4 vdst, vaddr, saddr offset13s glc slc global_load_sbyte vdst:opt, vaddr, saddr offset13s glc slc lds global_load_sbyte_d16 vdst, vaddr, saddr offset13s glc slc global_load_sbyte_d16_hi vdst, vaddr, saddr offset13s glc slc global_load_short_d16 vdst, vaddr, saddr offset13s glc slc global_load_short_d16_hi vdst, vaddr, saddr offset13s glc slc global_load_sshort vdst:opt, vaddr, saddr offset13s glc slc lds global_load_ubyte vdst:opt, vaddr, saddr offset13s glc slc lds global_load_ubyte_d16 vdst, vaddr, saddr offset13s glc slc global_load_ubyte_d16_hi vdst, vaddr, saddr offset13s glc slc global_load_ushort vdst:opt, vaddr, saddr offset13s glc slc lds global_store_byte vaddr, vdata, saddr offset13s glc slc global_store_byte_d16_hi vaddr, vdata, saddr offset13s glc slc global_store_dword vaddr, vdata, saddr offset13s glc slc global_store_dwordx2 vaddr, vdata, saddr offset13s glc slc global_store_dwordx3 vaddr, vdata, saddr offset13s glc slc global_store_dwordx4 vaddr, vdata, saddr offset13s glc slc global_store_short vaddr, vdata, saddr offset13s glc slc global_store_short_d16_hi vaddr, vdata, saddr offset13s glc slc scratch_load_dword vdst:opt, vaddr, saddr offset13s glc slc lds scratch_load_dwordx2 vdst, vaddr, saddr offset13s glc slc scratch_load_dwordx3 vdst, vaddr, saddr offset13s glc slc scratch_load_dwordx4 vdst, vaddr, saddr offset13s glc slc scratch_load_sbyte vdst:opt, vaddr, saddr offset13s glc slc lds scratch_load_sbyte_d16 vdst, vaddr, saddr offset13s glc slc scratch_load_sbyte_d16_hi vdst, vaddr, saddr offset13s glc slc scratch_load_short_d16 vdst, vaddr, saddr offset13s glc slc scratch_load_short_d16_hi vdst, vaddr, saddr offset13s glc slc scratch_load_sshort vdst:opt, vaddr, saddr offset13s glc slc lds scratch_load_ubyte vdst:opt, vaddr, saddr offset13s glc slc lds scratch_load_ubyte_d16 vdst, vaddr, saddr offset13s glc slc scratch_load_ubyte_d16_hi vdst, vaddr, saddr offset13s glc slc scratch_load_ushort vdst:opt, vaddr, saddr offset13s glc slc lds scratch_store_byte vaddr, vdata, saddr offset13s glc slc scratch_store_byte_d16_hi vaddr, vdata, saddr offset13s glc slc scratch_store_dword vaddr, vdata, saddr offset13s glc slc scratch_store_dwordx2 vaddr, vdata, saddr offset13s glc slc scratch_store_dwordx3 vaddr, vdata, saddr offset13s glc slc scratch_store_dwordx4 vaddr, vdata, saddr offset13s glc slc scratch_store_short vaddr, vdata, saddr offset13s glc slc scratch_store_short_d16_hi vaddr, vdata, saddr offset13s glc slc
MIMG¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS ———————————————————————————————————————————————————————————————————————————————————————————————————————— image_atomic_add vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_and vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_cmpswap vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_dec vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_inc vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_or vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_smax vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_smin vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_sub vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_swap vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_umax vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_umin vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_atomic_xor vdata:dst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_get_resinfo vdst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_load vdst, vaddr, srsrc dmask unorm glc slc a16 lwe da d16 image_load_mip vdst, vaddr, srsrc dmask unorm glc slc a16 lwe da d16 image_load_mip_pck vdst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_load_mip_pck_sgn vdst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_load_pck vdst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_load_pck_sgn vdst, vaddr, srsrc dmask unorm glc slc a16 lwe da image_sample vdst, vaddr, srsrc, ssamp dmask unorm glc slc a16 lwe da d16 image_store vdata, vaddr, srsrc dmask unorm glc slc a16 lwe da d16 image_store_mip vdata, vaddr, srsrc dmask unorm glc slc a16 lwe da d16 image_store_mip_pck vdata, vaddr, srsrc dmask unorm glc slc a16 lwe da image_store_pck vdata, vaddr, srsrc dmask unorm glc slc a16 lwe da
MTBUF¶
INSTRUCTION DST SRC0 SRC1 SRC2 SRC3 MODIFIERS —————————————————————————————————————————————————————————————————————————————————————————————————————— tbuffer_load_format_d16_x vdst, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_load_format_d16_xy vdst, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_load_format_d16_xyz vdst, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_load_format_d16_xyzw vdst, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_load_format_x vdst, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_load_format_xy vdst, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_load_format_xyz vdst, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_load_format_xyzw vdst, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_store_format_d16_x vdata, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_store_format_d16_xy vdata, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_store_format_d16_xyz vdata, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_store_format_d16_xyzw vdata, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_store_format_x vdata, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_store_format_xy vdata, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_store_format_xyz vdata, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc tbuffer_store_format_xyzw vdata, vaddr, srsrc, soffset fmt idxen offen offset12 glc slc
MUBUF¶
INSTRUCTION DST SRC0 SRC1 SRC2 SRC3 MODIFIERS —————————————————————————————————————————————————————————————————————————————————————————————————————————————————— buffer_atomic_add vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_add_f32 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_add_f64 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_add_x2 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_and vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_and_x2 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_cmpswap vdata:dst:b32x2, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_cmpswap_x2 vdata:dst:b64x2, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_dec vdata:dst:u32, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_dec_x2 vdata:dst:u64, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_inc vdata:dst:u32, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_inc_x2 vdata:dst:u64, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_max_f64 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_min_f64 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_or vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_or_x2 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_pk_add_f16 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_smax vdata:dst:i32, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_smax_x2 vdata:dst:i64, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_smin vdata:dst:i32, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_smin_x2 vdata:dst:i64, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_sub vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_sub_x2 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_swap vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_swap_x2 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_umax vdata:dst:u32, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_umax_x2 vdata:dst:u64, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_umin vdata:dst:u32, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_umin_x2 vdata:dst:u64, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_xor vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_atomic_xor_x2 vdata:dst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_invl2 buffer_load_dword vdst:opt, vaddr, srsrc, soffset idxen offen offset12 glc slc lds buffer_load_dwordx2 vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_dwordx3 vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_dwordx4 vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_format_d16_hi_x vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_format_d16_x vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_format_d16_xy vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_format_d16_xyz vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_format_d16_xyzw vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_format_x vdst:opt, vaddr, srsrc, soffset idxen offen offset12 glc slc lds buffer_load_format_xy vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_format_xyz vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_format_xyzw vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_sbyte vdst:opt, vaddr, srsrc, soffset idxen offen offset12 glc slc lds buffer_load_sbyte_d16 vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_sbyte_d16_hi vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_short_d16 vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_short_d16_hi vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_sshort vdst:opt, vaddr, srsrc, soffset idxen offen offset12 glc slc lds buffer_load_ubyte vdst:opt, vaddr, srsrc, soffset idxen offen offset12 glc slc lds buffer_load_ubyte_d16 vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_ubyte_d16_hi vdst, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_load_ushort vdst:opt, vaddr, srsrc, soffset idxen offen offset12 glc slc lds buffer_store_byte vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_byte_d16_hi vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_dword vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_dwordx2 vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_dwordx3 vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_dwordx4 vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_format_d16_hi_x vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_format_d16_x vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_format_d16_xy vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_format_d16_xyz vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_format_d16_xyzw vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_format_x vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_format_xy vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_format_xyz vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_format_xyzw vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_lds_dword srsrc, soffset offset12 lds buffer_store_short vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_store_short_d16_hi vdata, vaddr, srsrc, soffset idxen offen offset12 glc slc buffer_wbinvl1 buffer_wbinvl1_vol buffer_wbl2
SMEM¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS ———————————————————————————————————————————————————————————————————————————————————————————————— s_atc_probe probe, sbase, soffset offset21s s_atc_probe_buffer probe, sbase, soffset offset20u s_atomic_add sdata:dst, sbase, soffset offset21s glc s_atomic_add_x2 sdata:dst, sbase, soffset offset21s glc s_atomic_and sdata:dst, sbase, soffset offset21s glc s_atomic_and_x2 sdata:dst, sbase, soffset offset21s glc s_atomic_cmpswap sdata:dst:b32x2, sbase, soffset offset21s glc s_atomic_cmpswap_x2 sdata:dst:b64x2, sbase, soffset offset21s glc s_atomic_dec sdata:dst:u32, sbase, soffset offset21s glc s_atomic_dec_x2 sdata:dst:u64, sbase, soffset offset21s glc s_atomic_inc sdata:dst:u32, sbase, soffset offset21s glc s_atomic_inc_x2 sdata:dst:u64, sbase, soffset offset21s glc s_atomic_or sdata:dst, sbase, soffset offset21s glc s_atomic_or_x2 sdata:dst, sbase, soffset offset21s glc s_atomic_smax sdata:dst:i32, sbase, soffset offset21s glc s_atomic_smax_x2 sdata:dst:i64, sbase, soffset offset21s glc s_atomic_smin sdata:dst:i32, sbase, soffset offset21s glc s_atomic_smin_x2 sdata:dst:i64, sbase, soffset offset21s glc s_atomic_sub sdata:dst, sbase, soffset offset21s glc s_atomic_sub_x2 sdata:dst, sbase, soffset offset21s glc s_atomic_swap sdata:dst, sbase, soffset offset21s glc s_atomic_swap_x2 sdata:dst, sbase, soffset offset21s glc s_atomic_umax sdata:dst:u32, sbase, soffset offset21s glc s_atomic_umax_x2 sdata:dst:u64, sbase, soffset offset21s glc s_atomic_umin sdata:dst:u32, sbase, soffset offset21s glc s_atomic_umin_x2 sdata:dst:u64, sbase, soffset offset21s glc s_atomic_xor sdata:dst, sbase, soffset offset21s glc s_atomic_xor_x2 sdata:dst, sbase, soffset offset21s glc s_buffer_atomic_add sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_add_x2 sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_and sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_and_x2 sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_cmpswap sdata:dst:b32x2, sbase, soffset offset20u glc s_buffer_atomic_cmpswap_x2 sdata:dst:b64x2, sbase, soffset offset20u glc s_buffer_atomic_dec sdata:dst:u32, sbase, soffset offset20u glc s_buffer_atomic_dec_x2 sdata:dst:u64, sbase, soffset offset20u glc s_buffer_atomic_inc sdata:dst:u32, sbase, soffset offset20u glc s_buffer_atomic_inc_x2 sdata:dst:u64, sbase, soffset offset20u glc s_buffer_atomic_or sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_or_x2 sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_smax sdata:dst:i32, sbase, soffset offset20u glc s_buffer_atomic_smax_x2 sdata:dst:i64, sbase, soffset offset20u glc s_buffer_atomic_smin sdata:dst:i32, sbase, soffset offset20u glc s_buffer_atomic_smin_x2 sdata:dst:i64, sbase, soffset offset20u glc s_buffer_atomic_sub sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_sub_x2 sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_swap sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_swap_x2 sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_umax sdata:dst:u32, sbase, soffset offset20u glc s_buffer_atomic_umax_x2 sdata:dst:u64, sbase, soffset offset20u glc s_buffer_atomic_umin sdata:dst:u32, sbase, soffset offset20u glc s_buffer_atomic_umin_x2 sdata:dst:u64, sbase, soffset offset20u glc s_buffer_atomic_xor sdata:dst, sbase, soffset offset20u glc s_buffer_atomic_xor_x2 sdata:dst, sbase, soffset offset20u glc s_buffer_load_dword sdst, sbase, soffset offset20u glc s_buffer_load_dwordx16 sdst, sbase, soffset offset20u glc s_buffer_load_dwordx2 sdst, sbase, soffset offset20u glc s_buffer_load_dwordx4 sdst, sbase, soffset offset20u glc s_buffer_load_dwordx8 sdst, sbase, soffset offset20u glc s_buffer_store_dword sdata, sbase, soffset offset20u glc s_buffer_store_dwordx2 sdata, sbase, soffset offset20u glc s_buffer_store_dwordx4 sdata, sbase, soffset offset20u glc s_dcache_discard sbase, soffset offset21s s_dcache_discard_x2 sbase, soffset offset21s s_dcache_inv s_dcache_inv_vol s_dcache_wb s_dcache_wb_vol s_load_dword sdst, sbase, soffset offset21s glc s_load_dwordx16 sdst, sbase, soffset offset21s glc s_load_dwordx2 sdst, sbase, soffset offset21s glc s_load_dwordx4 sdst, sbase, soffset offset21s glc s_load_dwordx8 sdst, sbase, soffset offset21s glc s_memrealtime sdst:b64 s_memtime sdst:b64 s_scratch_load_dword sdst, sbase, soffset offset21s glc s_scratch_load_dwordx2 sdst, sbase, soffset offset21s glc s_scratch_load_dwordx4 sdst, sbase, soffset offset21s glc s_scratch_store_dword sdata, sbase, soffset offset21s glc s_scratch_store_dwordx2 sdata, sbase, soffset offset21s glc s_scratch_store_dwordx4 sdata, sbase, soffset offset21s glc s_store_dword sdata, sbase, soffset offset21s glc s_store_dwordx2 sdata, sbase, soffset offset21s glc s_store_dwordx4 sdata, sbase, soffset offset21s glc
SOP1¶
INSTRUCTION DST SRC ——————————————————————————————————————————————————— s_abs_i32 sdst, ssrc s_and_saveexec_b64 sdst, ssrc s_andn1_saveexec_b64 sdst, ssrc s_andn1_wrexec_b64 sdst, ssrc s_andn2_saveexec_b64 sdst, ssrc s_andn2_wrexec_b64 sdst, ssrc s_bcnt0_i32_b32 sdst, ssrc s_bcnt0_i32_b64 sdst, ssrc s_bcnt1_i32_b32 sdst, ssrc s_bcnt1_i32_b64 sdst, ssrc s_bitreplicate_b64_b32 sdst, ssrc s_bitset0_b32 sdst, ssrc s_bitset0_b64 sdst, ssrc:b32 s_bitset1_b32 sdst, ssrc s_bitset1_b64 sdst, ssrc:b32 s_brev_b32 sdst, ssrc s_brev_b64 sdst, ssrc s_cbranch_join ssrc s_cmov_b32 sdst, ssrc s_cmov_b64 sdst, ssrc s_ff0_i32_b32 sdst, ssrc s_ff0_i32_b64 sdst, ssrc s_ff1_i32_b32 sdst, ssrc s_ff1_i32_b64 sdst, ssrc s_flbit_i32 sdst, ssrc s_flbit_i32_b32 sdst, ssrc s_flbit_i32_b64 sdst, ssrc s_flbit_i32_i64 sdst, ssrc s_getpc_b64 sdst s_mov_b32 sdst, ssrc s_mov_b64 sdst, ssrc s_movreld_b32 sdst, ssrc s_movreld_b64 sdst, ssrc s_movrels_b32 sdst, ssrc s_movrels_b64 sdst, ssrc s_nand_saveexec_b64 sdst, ssrc s_nor_saveexec_b64 sdst, ssrc s_not_b32 sdst, ssrc s_not_b64 sdst, ssrc s_or_saveexec_b64 sdst, ssrc s_orn1_saveexec_b64 sdst, ssrc s_orn2_saveexec_b64 sdst, ssrc s_quadmask_b32 sdst, ssrc s_quadmask_b64 sdst, ssrc s_rfe_b64 ssrc s_set_gpr_idx_idx ssrc s_setpc_b64 ssrc s_sext_i32_i16 sdst, ssrc s_sext_i32_i8 sdst, ssrc s_swappc_b64 sdst, ssrc s_wqm_b32 sdst, ssrc s_wqm_b64 sdst, ssrc s_xnor_saveexec_b64 sdst, ssrc s_xor_saveexec_b64 sdst, ssrc
SOP2¶
INSTRUCTION DST SRC0 SRC1 —————————————————————————————————————————————————————————————— s_absdiff_i32 sdst, ssrc0, ssrc1 s_add_i32 sdst, ssrc0, ssrc1 s_add_u32 sdst, ssrc0, ssrc1 s_addc_u32 sdst, ssrc0, ssrc1 s_and_b32 sdst, ssrc0, ssrc1 s_and_b64 sdst, ssrc0, ssrc1 s_andn2_b32 sdst, ssrc0, ssrc1 s_andn2_b64 sdst, ssrc0, ssrc1 s_ashr_i32 sdst, ssrc0, ssrc1:u32 s_ashr_i64 sdst, ssrc0, ssrc1:u32 s_bfe_i32 sdst, ssrc0, ssrc1:u32 s_bfe_i64 sdst, ssrc0, ssrc1:u32 s_bfe_u32 sdst, ssrc0, ssrc1 s_bfe_u64 sdst, ssrc0, ssrc1:u32 s_bfm_b32 sdst, ssrc0, ssrc1 s_bfm_b64 sdst, ssrc0:b32, ssrc1:b32 s_cbranch_g_fork ssrc0, ssrc1 s_cselect_b32 sdst, ssrc0, ssrc1 s_cselect_b64 sdst, ssrc0, ssrc1 s_lshl1_add_u32 sdst, ssrc0, ssrc1 s_lshl2_add_u32 sdst, ssrc0, ssrc1 s_lshl3_add_u32 sdst, ssrc0, ssrc1 s_lshl4_add_u32 sdst, ssrc0, ssrc1 s_lshl sdst, src1:u32 s_lshl_b64 dst_sel dst_unused dst_sel dst_unused src0_sel v_cvt_u32_f32 dst_sel vdst, src v_log_legacy_f32_dpp vdst, vsrc:m m, vsrc1:src v_log_legacy_f32_dpp src v_log_legacy_f32_dpp 0ab ssrc1 s_lshl4_add_u32 sdst, ssrc0, omod src:src1 v_cmpx_f_u64_e64 bank_ v_cmpx_f_u32_e64 s class="reference internal" href="gfx9_src_d578c4.html#amdgpu-synid-gfx9-tml#amdgpu-synid-gfx9-vdst-89680f">vdst, src0, s class="reference internal" href="gfx9_src_internal" href="../AMDGPUModifierSyntref">omod ssrc1 s_cmp_eq_u64 ssrc0, #amdgpu-synid-clamp"ierSyntax.html#amdgpu-synid-clamp"ierSyntax.html#amdgpu-synid-clamp"ierSyntax.html#amdgpu-synid-clamp"ierSyntax.html#amdgpu-synid-clamp"ierSynt/a> v_cmp_le_f64_e64 s class="reference internal" href="gfx9_src_d578c4-ref">src1 v_cmpx_f_u64_e64 bank_ v_cmpx_f_u32_e64 vdst, src:src0, s class="reference internal" href="gfx9_src_internal" href="../AMDGPUModifierSyntref">omod ssrynid-clrc1-sel">src1_sel v_subrev_u16 rc-c5d631">ssrc1 s_bfe_u64 sdst, src:ssrc1:ssrynid-clrc1-sel">src1_sel v_subrev_u16 rc-c5d631">ssrc1 s_bfe73ab34.html#amdgpu-synid-gfx9-src-73ab34">9-m-c141fc">m clamp v_cmp_eq_f32_e64 mdgpu-synid-glc">glc s_buffer_atomic_umax sdata:vsrc:m vdst, src0:m, row_masksrc v_exp_legacy_f32_dpp vdst<1 v_subrev_f16_dpp 9-m-c141fc">m reference internal" href="gfx9_vsrc_6802ce.html#amdgpu-synid-gfx9-vsrintern bank_mask bound_ctrl v_cvt_f32_f16_sdwa vdstu16, vsrc1 v_ashrrev_i16_dpp vsstd-ref">u16, u16, vsrc1 vsrc1, bank_mask vsrc1 v_ashrrev_i16_dpp vsstd-ref">u16, u16, vsrc1v_ashrrev_i16_dpp 9-m-c141fc">vsro1, ssrc s_brev_b64 vdstu16, vsrc1 v_ashrrev_i16_dpp u16, vsrc1 :9-m-c141fc">vsro1m, vsrc0:m, vsrc1:i16 dpp_ctrl row_mask bank_mask bound_ctrlvsro1:srsrc, ssamp sdst, src:m clamp vsrc1 v_ashrrev_i16_dpp 9-m-c141fc">vsro1src v_cvt_norm_i16_f16 vdst, src v_cvt_norm_i16_f16_dpp vdst, vsrc:vsrc1 mv_ashrrev_i16_dpp 9-m-c141fc">vsro1vdst, vsrc:src v_cvt_norm_i16_f16_dpp "gfx9_vsrc_6802ce.html#amdgpu-synid-gfx9-vsrc-6802ce">src src0, src1, l" href="gfx9_m_c141fc.html#amdgpu-synid-gfx9-m-c141fc">m, src1class="reference internal" href="gfx9_src_d578c4.html#amdgpu-synid-gfx9-src-d578c4">src:omospan> v_interp_p1_f32 omod dst_sel m, src0:m, src1:dst_sel clamp v_cmp_gt_f32_e64 sdst, src"../AMDGPUModifierSyntax.html#amdgpu-synid-omod">omospan> v_interp_p1_f32 ">da d16 image_sample_l src clamp , src1vdst, src clamp omod .html#amdgpu-synid-gfx9-m-c141fc">m, src1class="reference internal" href="gfx9_src_d578c4.html#amdgpu-synid-gfx9-src-d578c4">src: dst_sel image_sample_l src clamp m 3aa class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-clamp">clamp v_cmp_u_f64_e64 src: omod .html#amdgpu-synidrc_d95796.html#amdgpu-synid-gfx9-src-d95796">src1:m span> d16 dst_unused clamp v_cmp_u_f64_e64 f">src clamp omod .html#amdgpu-synidrc_d95796.html#amdgpu-synid-gfx9-src-d95796">src1:m clamp src: src src1:dst_unused m span> dst_unused dst_unused clamp v_cmp_u_f64_ef">src clamp srcef">src0_sel src1_sel v_sub_f32_sdwa vdst, offset12s sdst, slc m, src1:vdst, saddr vdst ,vdst , src s_buffer_atomic_dec src s_buffer_atomic_dec src s_buffer_atomic_dec sdst, vdst, clamp v_cmp_nlt_f16_e64 src s_buffer_atomic_dec src s_buffer_atomic_dec ss="reference internal" href="gfx9_vdst_89680f.html#amdgpu-synid-gfx9-vdst-89680f">vdst, <.html#amdgpu-synid-gfx9-vsrc-6802ce">vsrc< clamp omod v_div_fixup_f32 vdst, , , , , a>, vcc, src0, , , , , iu8x4, ,vcc, , , , , , vcc, src0, , , , a>, vcc, src0, , , , a>, vcc, , , , vcc, <.html#amdgpu-synid-gfx9-vsrc-6802ce">n class="std std-ref">clamp v_cmp_o_f16_e64 omod v_div_fixup_f32 vdst, x9_src_e1561c.html#amdgpu-synid-gfx9-src-e1561c">src0, , , m hrreference internal" href="gfx9_src_e1561c.html#amdgpu-synid class="referencssrcsrc0, vsrc1 v_cmp_eq_u16 vcc, , omod v_div_fixup_f32 vdst, x9_src_e1561c cz8axrmdgpu-synid-gfx9-src-e1561c">src0, , , m hrreference internal" href="gfx9_src_e1561c.html#amdgpu-synid class="referencssrcvcc, ,
