Syntax of AMDGPU Instruction Operands¶
Conventions¶
The following notation is used throughout this document:
Notation
Description
{0..N}
Any integer value in the range from 0 to N (inclusive).
<x>
Syntax and meaning of x is explained elsewhere.
Operands¶
v¶
Vector registers. There are 256 32-bit vector registers.
A sequence of vector registers may be used to operate with more than 32 bits of data.
Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 8, 16 and 32 vector registers.
Syntax
Description
v<N>
A single 32-bit vector register.
N must be a decimal integer number.
v[<N>]
A single 32-bit vector register.
N may be specified as an integer number or an absolute expression.
v[<N>:<K>]
A sequence of (K-N+1) vector registers.
N and K may be specified as integer numbers or absolute expressions.
[v<N>, v<N+1>, … v<K>]
A sequence of (K-N+1) vector registers.
Register indices must be specified as decimal integer numbers.
Note: N and K must satisfy the following conditions:
N <= K.
0 <= N <= 255.
0 <= K <= 255.
K-N+1 must be equal to 1, 2, 3, 4, 5, 6, 8, 16 or 32.
GFX90A has an additional alignment requirement: pairs of vector registers must be even-aligned (first register must be even).
Examples:
v255
v[0]
v[0:1]
v[1:1]
v[0:3]
v[2*2]
v[1-1:2-1]
[v252]
[v252,v253,v254,v255]
GFX10 Image instructions may use special NSA (Non-Sequential Address) syntax for image addresses:
Syntax
Description
[Vm, Vn, … Vk]
A sequence of 32-bit vector registers. Each register may be specified using syntax defined above.
In contrast with standard syntax, registers in NSA sequence are not required to have consecutive indices. Moreover, the same register may appear in the list more than once.
Examples:
[v32,v1,v[2]]
[v[32],v[1:1],[v2]]
[v4,v4,v4,v4]
a¶
Accumulator registers. There are 256 32-bit accumulator registers.
A sequence of accumulator registers may be used to operate with more than 32 bits of data.
Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 8, 16 and 32 accumulator registers.
Syntax
An Alternative Syntax (SP3)
Description
a<N>
acc<N>
A single 32-bit accumulator register.
N must be a decimal integer number.
a[<N>]
acc[<N>]
A single 32-bit accumulator register.
N may be specified as an integer number or an absolute expression.
a[<N>:<K>]
acc[<N>:<K>]
A sequence of (K-N+1) accumulator registers.
N and K may be specified as integer numbers or absolute expressions.
[a<N>, a<N+1>, … a<K>]
[acc<N>, acc<N+1>, … acc<K>]
A sequence of (K-N+1) accumulator registers.
Registe