\page graniterapids Intel® GraniteRapids

This page is valid for GraniteRapids.

# Available performance monitors for the Intel® GraniteRapids microarchitecture

- \ref GNR_FIXED "Fixed-purpose counters"
- \ref GNR_METRICS "Performance metric counters"
- \ref GNR_PMC "General-purpose counters"
- \ref GNR_THERMAL "Thermal counters"
- \ref GNR_VOLTAGE "Core voltage counters"
- \ref GNR_POWER "Power measurement counters"
- \ref GNR_UBOX "Uncore global counters"
- \ref GNR_CBOX "Last level cache counters"
- \ref GNR_MBOX "Memory channel counters"
- \ref GNR_WBOX "Power control unit counters"
- \ref GNR_QBOX "UPI interface counters"
- \ref GNR_RBOX "Mesh-to-UPI counters (B2UPI)"
- \ref GNR_IBOX "IIO box counters"
- \ref GNR_BBOX "Mesh2Memory counters (B2CMI)"
- \ref GNR_PBOX "Mesh2PCIe counters (B2CXL)"
- \ref GNR_IRP "IIO ring port counters (IRP)"
- \ref GNR_MDF "Embedded multi-die interconnect bridge (MDF)"

# Counters available for each hardware thread

\anchor GNR_FIXED

## Fixed-purpose counters

Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose counters. Each can measure only one specific event. The Intel® GraniteRapids architecture adds a fourth fixed-purpose counter for the event TOPDOWN_SLOTS.

### Counter and events

Counter name | Event name
--- | ---
FIXC0 | INSTR_RETIRED_ANY
FIXC1 | CPU_CLK_UNHALTED_CORE
FIXC2 | CPU_CLK_UNHALTED_REF
FIXC3 | TOPDOWN_SLOTS

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
anythread | N | Set bit 2+(index*4) in config register |
kernel | N | Set bit (index*4) in config register |

\anchor GNR_METRICS

## Performance metric counters

With the Intel® Granite Rapids microarchitecture a new class of core-local counters was introduced, the so-called perf-metrics. The reflect the first level of the Top-down Microarchitecture Analysis tree. The events return the fraction of slots used by the event. With Intel SapphireRapids, four additional events have been added that partly reflect the second level of the TMA tree. The metrics are only supported when built with `ACCESSMODE=accessdaemon` or `ACCESSMODE=direct`.

### Counter and events

Counter name | Event name
--- | ---
TMA0 | RETIRING
TMA1 | BAD_SPECULATION
TMA2 | FRONTEND_BOUND
TMA3 | BACKEND_BOUND
TMA4 | HEAVY_OPS
TMA5 | BR_MIEMREDICT
TMA6 | FETCH_LATENCY
TMA7 | MEM_BOUND

\anchor GNR_PMC

## General-purpose counters

Commonly the Intel® GraniteRapids microarchitecture provides 4 general-purpose counters consisting of a config and a counter register.

### Counter and events

Counter name | Event name
--- | ---
PMC0 |
PMC1 |
PMC2 |
PMC3 |
PMC4 | *
PMC5 | *
PMC6 | *
PMC7 | *

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
kernel | N | Set bit 17 in config register |
anythread | N | Set bit 21 in config register | The anythread option is deprecated but still supported. Please check the official Intel® documentation how to use the option properly.
threshold | 8 bit hex value | Set bits 24-31 in config register |
invert | N | Set bit 23 in config register |
in_transaction | N | Set bit 32 in config register | Only available if Intel® Transactional Synchronization Extensions are available
in_transaction_aborted | N | Set bit 33 in config register | Only counter PMC2 and only if Intel® Transactional Synchronization Extensions are available

If HyperThreading is disabled, each core can use 8 general-purpose counters named PMC<4-7>. \anchor GNR_THERMAL

## Thermal counters

The Intel® GraniteRapids microarchitecture provides one register for the current core temperature.

### Counter and events

Counter name | Event name
--- | ---
TMP0 | TEMP_CORE

\anchor GNR_VOLTAGE

## Core voltage counters

The Intel® GraniteRapids microarchitecture provides one register for the current core voltage.

### Counter and events

Counter name | Event name
--- | ---
VTG0 | VOLTAGE_CORE

# Counters available for one hardware thread per socket

\anchor GNR_POWER

## Power counter

The Intel® Granite Rapids microarchitecture provides measurements of the current power consumption through the RAPL interface.

### Counter and events

Counter name | Event name
--- | ---
PWR0 | PWR_PKG_ENERGY
PWR1 | PWR_PP0_ENERGY
PWR2 | PWR_PP1_ENERGY
PWR3 | PWR_DRAM_ENERGY
PWR4 | PWR_PLATFORM_ENERGY

\anchor GNR_UBOX

## Uncore global counters

The Intel® GraniteRapids microarchitecture provides measurements for the global uncore.

### Counter and events

Counter name | Event name
--- | ---
UBOX0 | *
UBOX1 | *

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
threshold | 8 bit hex value | Set bits 24-31 in config register |
invert | N | Set bit 23 in config register |

\anchor GNR_CBOX

## Last level cache counters

The Intel® GraniteRapids microarchitecture provides measurements for the last level cache segments.

### Counter and events

Counter name | Event name
--- | ---
CBOX<0-125>C0 | *
CBOX<0-125>C1 | *
CBOX<0-125>C2 | *
CBOX<0-125>C3 | *

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
threshold | 8 bit hex value | Set bits 24-28 in config register |
invert | N | Set bit 23 in config register |

\anchor GNR_MBOX

## Memory channel counters

The Intel® GraniteRapids microarchitecture provides measurements of the memory channels of each integrated Memory Controllers (iMC) in the Uncore.
The integrated Memory Controllers performance counters are exposed to the operating system through MMIO interfaces.

### Counter and events

Counter name | Event name
--- | ---
MBOX<0-11>C0 | *
MBOX<0-11>C1 | *
MBOX<0-11>C2 | *
MBOX<0-11>C3 | *

### Available Options

Option | Argument | Operation | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
invert | N | Set bit 23 in config register |
threshold | 8 bit hex value | Set bits 24-31 in config register |

\anchor GNR_WBOX

## Power control unit counters

The Intel® GraniteRapids microarchitecture provides measurements of the power control unit (PCU) in the Uncore.
The PCU performance counters are exposed to the operating system through the MSR interface. The name WBOX originates from the Nehalem EX Uncore monitoring where those functional units are called WBOX.

### Counter and events

Counter name | Event name
--- | ---
PCU<0-4>C0 | *
PCU<0-4>C1 | *
PCU<0-4>C2 | *
PCU<0-4>C3 | *

### Available Options

Option | Argument | Operation | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
invert | N | Set bit 23 in config register |
threshold | 5 bit hex value | Set bits 24-28 in config register |

\anchor GNR_QBOX

## UPI interface counters

The Intel® GraniteRapids microarchitecture provides measurements of the Ultra Path Interconnect Link layer (UPI LL) in the Uncore.

### Counter and events

Counter name | Event name
--- | ---
UPI<0-5>C0 | *
UPI<0-5>C1 | *
UPI<0-5>C2 | *
UPI<0-5>C3 | *

### Available Options

Option | Argument | Operation | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
invert | N | Set bit 23 in config register |
threshold | 8 bit hex value | Set bits 24-31 in config register |

\anchor GNR_RBOX

## Mesh-to-UPI counters (B2UPI)

The Intel® GraniteRapids microarchitecture provides measurements of the Mesh-to-UPI (B2UPI) interface in the Uncore.

### Counter and events

Counter name | Event name
--- | ---
RBOX<0-5>C0 | *
RBOX<0-5>C1 | *
RBOX<0-5>C2 | *
RBOX<0-5>C3 | *

### Available Options

Option | Argument | Operation | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
invert | N | Set bit 23 in config register |
threshold | 8 bit hex value | Set bits 24-31 in config register |

\anchor GNR_IBOX

## IIO box counters

The Intel® GraniteRapids microarchitecture provides measurements of the IIO box in the Uncore.
The IIO box counters are exposed to the operating system through the MSR interface.

### Counter and events

Counter name | Event name
--- | ---
IBOX<0-15>C0 | *
IBOX<0-15>C1 | *
IBOX<0-15>C2 | *
IBOX<0-15>C3 | *

### Available Options

Option | Argument | Operation | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
invert | N | Set bit 23 in config register |
threshold | 8 bit hex value | Set bits 24-31 in config register |

\anchor GNR_BBOX

## Mesh2Memory counters (B2CMI)

The Intel® GraniteRapids microarchitecture provides measurements of the mesh B2CMI which connects the cores with the Uncore memory controllers devices.

### Counter and events

Counter name | Event name
--- | ---
M2M<0-5>C0 | *
M2M<0-5>C1 | *
M2M<0-5>C2 | *
M2M<0-5>C3 | *

### Available Options

Option | Argument | Operation | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
invert | N | Set bit 23 in config register |
threshold | 5 bit hex value | Set bits 24-28 in config register |

\anchor GNR_PBOX

## Mesh2CXL counters (B2CXL)

The Intel® Granite Rapids microarchitecture provides measurements of the mesh to the IIO devices.

### Counter and events

Counter name | Event name
--- | ---
PBOX<0-5>C0 | *
PBOX<0-5>C1 | *
PBOX<0-5>C2 | *
PBOX<0-5>C3 | *

### Available Options

Option | Argument | Operation | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
invert | N | Set bit 23 in config register |
threshold | 5 bit hex value | Set bits 24-28 in config register |

\anchor GNR_IRP

## IIO ring ports counters (IRP)

The Intel® Granite Rapids microarchitecture provides measurements of the IIO ring ports.

### Counter and events

Counter name | Event name
--- | ---
IRP<0-15>C0 | *
IRP<0-15>C1 | *
IRP<0-15>C2 | *
IRP<0-15>C3 | *

### Available Options

Option | Argument | Operation | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
invert | N | Set bit 23 in config register |
threshold | 5 bit hex value | Set bits 24-28 in config register |

\anchor GNR_MDF

## Embedded Multi-die Interconnect Bridge (MDF)

The Intel® Granite Rapids microarchitecture provides measurements of the embedded multi-die interconnect bridge.

### Counter and events

Counter name | Event name
--- | ---
MDF<0-79>C0 | *
MDF<0-79>C1 | *
MDF<0-79>C2 | *
MDF<0-79>C3 | *

### Available Options

Option | Argument | Operation | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
invert | N | Set bit 23 in config register |
threshold | 5 bit hex value | Set bits 24-28 in config register |