\page goldmont Intel® Goldmont/GoldmontPlus/Tremont

# Available performance monitors for the Intel® Goldmont microarchitecture

- \ref GLM_FIXED "Fixed-purpose counters"
- \ref GLM_PMC "General-purpose counters"
- \ref GLM_THERMAL "Thermal counters"
- \ref GLM_POWER "Power measurement counters"

# Counters available for each hardware thread

\anchor GLM_FIXED

## Fixed-purpose counters

Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose counters. Each can measure only one specific event.

### Counter and events

Counter name | Event name
--- | ---
FIXC0 | INSTR_RETIRED_ANY
FIXC1 | CPU_CLK_UNHALTED_CORE
FIXC2 | CPU_CLK_UNHALTED_REF

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
anythread | N | Set bit 2+(index*4) in config register |
kernel | N | Set bit (index*4) in config register |

\anchor GLM_PMC

## General-purpose counters

The Intel® Goldmont microarchitecture provides 4 general-purpose counters consisting of a config and a counter register.

### Counter and events

Counter name | Event name
--- | ---
PMC0 | *
PMC1 | *
PMC2 | *
PMC3 | *

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
kernel | N | Set bit 17 in config register |
threshold | 8 bit hex value | Set bits 24-31 in config register |
invert | N | Set bit 23 in config register |

### Special handling for events

The Intel® Goldmont microarchitecture provides measuring of offcore events in PMC counters. Therefore the stream of offcore events must be filtered using the OFFCORE_RESPONSE registers. The Intel® Goldmont microarchitecture has two of those registers. LIKWID defines some events that perform the filtering according to the event name. Although there are many bitmasks possible, LIKWID natively provides only the ones with response type ANY. Own filtering can be applied with the OFFCORE_RESPONSE_0_OPTIONS and OFFCORE_RESPONSE_1_OPTIONS events. Only OFFCORE_RESPONSE_0_OPTIONS can be used to measure average latencies. Only for those events two more counter options are available:

Option | Argument | Description | Comment
--- | --- | --- | ---
match0 | 16 bit hex value | Input value masked with 0xFFFF and written to bits 0-15 in the OFFCORE_RESPONSE register | Check the Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring and https://download.01.org/perfmon/GLM.
match1 | 22 bit hex value | Input value is written to bits 16-38 in the OFFCORE_RESPONSE register | Check the Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring and https://download.01.org/perfmon/GLM.

\anchor GLM_THERMAL

## Thermal counter

The Intel® Goldmont microarchitecture provides one register for the current core temperature.

### Counter and events

Counter name | Event name
--- | ---
TMP0 | TEMP_CORE

# Counters available for one hardware thread per socket

\anchor GLM_POWER

## Power counters

The Intel® Goldmont microarchitecture provides measurements of the current power consumption through the RAPL interface.

### Counter and events

Counter name | Event name
--- | ---
PWR0 | PWR_PKG_ENERGY
PWR1 | PWR_PP0_ENERGY
PWR2* | PWR_PP1_ENERGY
PWR3* | PWR_DRAM_ENERGY

*) The PWR2 and PWR3 counter is commonly not implemented by Intel® Goldmont systems.