\page icelake Intel® Icelake

This page is valid for Icelake. The Icelake microarchitecture supports the UBOX and the CBOX Uncore devices.

# Available performance monitors for the Intel® Icelake microarchitecture

- \ref ICL_FIXED "Fixed-purpose counters"
- \ref ICL_METRICS "Performance metric counters"
- \ref ICL_PMC "General-purpose counters"
- \ref ICL_THERMAL "Thermal counters"
- \ref ICL_VOLTAGE "Core voltage counters"
- \ref ICL_POWER "Power measurement counters"
- \ref ICL_UBOX "Uncore global counters"
- \ref ICL_CBOX "Last level cache counters"
- \ref ICL_MBOX "Memory controller counters"

# Counters available for each hardware thread

\anchor ICL_FIXED

## Fixed-purpose counters

Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose counters. Each can measure only one specific event. The Intel® Icelake architecture adds a fourth fixed-purpose counter for the event TOPDOWN_SLOTS.

### Counter and events

Counter name | Event name
--- | ---
FIXC0 | INSTR_RETIRED_ANY
FIXC1 | CPU_CLK_UNHALTED_CORE
FIXC2 | CPU_CLK_UNHALTED_REF
FIXC3 | TOPDOWN_SLOTS

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
anythread | N | Set bit 2+(index*4) in config register |
kernel | N | Set bit (index*4) in config register |

\anchor ICL_METRICS

## Performance metric counters

With the Intel® Icelake microarchitecture a new class of core-local counters was introduced, the so-called perf-metrics. The reflect the first level of the Top-down Microarchitecture Analysis tree. The events return the fraction of slots used by the event.

### Counter and events

Counter name | Event name
--- | ---
TMA0 | RETIRING
TMA1 | BAD_SPECULATION
TMA2 | FRONTEND_BOUND
TMA3 | BACKEND_BOUND

\anchor ICL_PMC

## General-purpose counters

Commonly the Intel® Icelake microarchitecture provides 4 general-purpose counters consisting of a config and a counter register.

### Counter and events

Counter name | Event name
--- | ---
PMC0 | *
PMC1 | *
PMC2 | *
PMC3 | *

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
kernel | N | Set bit 17 in config register |
anythread | N | Set bit 21 in config register | The anythread option is deprecated but still supported. Please check the official Intel® documentation how to use the option properly.
threshold | 8 bit hex value | Set bits 24-31 in config register |
invert | N | Set bit 23 in config register |
in_transaction | N | Set bit 32 in config register | Only available if Intel® Transactional Synchronization Extensions are available
in_transaction_aborted | N | Set bit 33 in config register | Only counter PMC2 and only if Intel® Transactional Synchronization Extensions are available

If HyperThreading is disabled, each core can use 8 general-purpose counters named <4-7>. \anchor ICL_THERMAL

## Thermal counters

The Intel® Icelake microarchitecture provides one register for the current core temperature.

### Counter and events

Counter name | Event name
--- | ---
TMP0 | TEMP_CORE

\anchor ICL_VOLTAGE

## Core voltage counters

The Intel® Icelake microarchitecture provides one register for the current core voltage.

### Counter and events

Counter name | Event name
--- | ---
VTG0 | VOLTAGE_CORE

# Counters available for one hardware thread per socket

\anchor ICL_POWER

## Power counter

The Intel® Icelake microarchitecture provides measurements of the current power consumption through the RAPL interface.

### Counter and events

Counter name | Event name
--- | ---
PWR0 | PWR_PKG_ENERGY
PWR1 | PWR_PP0_ENERGY
PWR2 | PWR_PP1_ENERGY
PWR3 | PWR_DRAM_ENERGY
PWR4 | PWR_PLATFORM_ENERGY

\anchor ICL_UBOX

## Uncore global counters

The Intel® Icelake microarchitecture provides measurements for the global uncore.

### Counter and events

Counter name | Event name
--- | ---
UBOX0 | *
UBOX1 | *
UBOXFIX | UNCORE_CLOCK

\anchor ICL_CBOX

## Last level cache counters

The Intel® Icelake microarchitecture provides measurements for the last level cache segments.

### Counter and events

Counter name | Event name
--- | ---
CBOX<0-3>C0 | *
CBOX<0-3>C1 | *

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
threshold | 8 bit hex value | Set bits 24-28 in config register |
invert | N | Set bit 23 in config register |

\anchor ICL_MBOX

## Memory controller counters

The Intel® Icelake microarchitecture provides measurements for the memory controller. The counters are free-running.

### Counter and events

Counter name | Event name
--- | ---
MBOX0C0 | IO_REQUESTS
MBOX0C1 | DRAM_READS
MBOX0C2 | DRAM_WRITES