# TCL File Generated by Component Editor 16.0
# Fri May 14 23:15:32 PDT 2021
# DO NOT MODIFY


# 
# wishbone_master "bladeRF NiOS Wishbone Master" v1.0
# Robert Ghilduta 2021.05.14.23:15:32
# NiOS Wishbone Master
# 

# 
# request TCL package from ACDS 16.0
# 
package require -exact qsys 16.0


# 
# module wishbone_master
# 
set_module_property DESCRIPTION "NiOS Wishbone Master"
set_module_property NAME wishbone_master
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP Peripherals
set_module_property AUTHOR "Robert Ghilduta"
set_module_property DISPLAY_NAME "bladeRF NiOS Wishbone Master"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL wishbone_master
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file wishbone_master.qip OTHER PATH ./wishbone_master.qip


# 
# parameters
# 
add_parameter ADDR_BITS INTEGER 32 ""
set_parameter_property ADDR_BITS DEFAULT_VALUE 32
set_parameter_property ADDR_BITS DISPLAY_NAME ADDR_BITS
set_parameter_property ADDR_BITS TYPE INTEGER
set_parameter_property ADDR_BITS UNITS None
set_parameter_property ADDR_BITS ALLOWED_RANGES -2147483648:2147483647
set_parameter_property ADDR_BITS DESCRIPTION ""
set_parameter_property ADDR_BITS HDL_PARAMETER true


add_parameter DATA_BITS INTEGER 32 ""
set_parameter_property DATA_BITS DEFAULT_VALUE 32
set_parameter_property DATA_BITS DISPLAY_NAME DATA_BITS
set_parameter_property DATA_BITS TYPE INTEGER
set_parameter_property DATA_BITS UNITS None
set_parameter_property DATA_BITS ALLOWED_RANGES -2147483648:2147483647
set_parameter_property DATA_BITS DESCRIPTION ""
set_parameter_property DATA_BITS HDL_PARAMETER true
# 
# display items
# 


# 
# connection point avalon_slave_0
# 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock_sink
set_interface_property avalon_slave_0 associatedReset reset
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 1
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
set_interface_property avalon_slave_0 EXPORT_OF ""
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""

add_interface_port avalon_slave_0 addr address Input 24
add_interface_port avalon_slave_0 din writedata Input 32
add_interface_port avalon_slave_0 dout readdata Output 32
add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 read read Input 1
add_interface_port avalon_slave_0 waitreq waitrequest Output 1
add_interface_port avalon_slave_0 readack readdatavalid Output 1
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock clock_sink
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset reset reset Input 1


# 
# connection point conduit_end
# 
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock clock_sink
set_interface_property conduit_end associatedReset reset
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""

add_interface_port conduit_end wb_clk_i wb_clk_i Input 1
add_interface_port conduit_end wb_rst_i wb_rst_i Input 1
add_interface_port conduit_end wb_adr_o wb_adr_o Output ADDR_BITS
add_interface_port conduit_end wb_dat_o wb_dat_o Output DATA_BITS
add_interface_port conduit_end wb_dat_i wb_dat_i Input DATA_BITS
add_interface_port conduit_end wb_we_o wb_we_o Output 1
add_interface_port conduit_end wb_sel_o wb_sel_o Output 1
add_interface_port conduit_end wb_stb_o wb_stb_o Output 1
add_interface_port conduit_end wb_ack_i wb_ack_i Input 1
add_interface_port conduit_end wb_cyc_o wb_cyc_o Output 1


# 
# connection point interrupt_sender
# 
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint ""
set_interface_property interrupt_sender associatedClock clock_sink
set_interface_property interrupt_sender associatedReset reset
set_interface_property interrupt_sender bridgedReceiverOffset ""
set_interface_property interrupt_sender bridgesToReceiver ""
set_interface_property interrupt_sender ENABLED true
set_interface_property interrupt_sender EXPORT_OF ""
set_interface_property interrupt_sender PORT_NAME_MAP ""
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""

add_interface_port interrupt_sender intr irq Output 1


# 
# connection point clock_sink
# 
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""

add_interface_port clock_sink clock clk Input 1
