// ***************************************************************************
// ***************************************************************************
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module ad_rst (

  // clock reset

  preset,
  clk,
  rst);

  // clock reset

  input           preset;
  input           clk;
  output          rst;

  // internal registers

  reg             ad_rst_sync_m1 = 'd0 /* synthesis preserve */;
  reg             ad_rst_sync = 'd0 /* synthesis preserve */;
  reg             rst = 'd0;

  // simple reset gen

  always @(posedge clk) begin
    ad_rst_sync_m1 <= preset;
    ad_rst_sync <= ad_rst_sync_m1;
    rst <= ad_rst_sync;
  end

endmodule

// ***************************************************************************
// ***************************************************************************
