###################################################################
##
## Name     : axi_ad7476
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN axi_ad7476

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:USER
OPTION DESC = axi_ad7476
OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
OPTION RUN_NGCBUILD = TRUE


## Bus Interfaces
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
BUS_INTERFACE BUS = S_AXIS_S2MM, BUS_STD = AXIS, BUS_TYPE = INITIATOR

## Generics for VHDL or Parameters for Verilog
PARAMETER PCORE_ID = 0, DT = INTEGER
PARAMETER PCORE_DEVICE_TYPE = 0, DT = INTEGER
PARAMETER PCORE_IODELAY_GROUP = adc_if_delay_group, DT = STRING
PARAMETER C_S_AXI_MIN_SIZE = 0x0000ffff, DT = std_logic_vector, BUS = S_AXI
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI, MIN_SIZE = 0x100
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
PARAMETER C_S_AXIS_S2MM_PROTOCOL = XIL_AXI_STREAM_ETH_DATA, DT = STRING, BUS = S_AXIS_S2MM, ASSIGNMENT = CONSTANT, TYPE = NON_HDL

## ADC Interface
## ADD USER PORTS HERE
PORT ref_clk = "", DIR = I, SIGIS = CLK
PORT rx_clk = "", DIR = I, SIGIS = CLK
PORT data_0_i = "", DIR = I
PORT data_1_i = "", DIR = I
PORT sclk_o = "", DIR = O, SIGIS = CLK
PORT cs_o = "", DIR = O


PORT adc_start_out = "", DIR = O
PORT dma_start_out = "", DIR = O
PORT adc_start_in = "", DIR = I
PORT dma_start_in = "", DIR = I

## Monitor Interface
PORT adc_clk = "", DIR = O
PORT adc_mon_valid = "", DIR = O
PORT adc_mon_data = "", DIR = O, VEC = [31:0]

## DMA Interface
PORT s_axis_s2mm_clk = "", DIR = I, SIGIS=CLK, BUS=S_AXIS_S2MM
PORT s_axis_s2mm_tvalid = TVALID, DIR = O, BUS=S_AXIS_S2MM
PORT s_axis_s2mm_tdata = TDATA, DIR = O, VEC = [31:0], BUS=S_AXIS_S2MM
PORT s_axis_s2mm_tkeep = TKEEP, DIR = O, VEC = [3:0], BUS=S_AXIS_S2MM
PORT s_axis_s2mm_tlast = TLAST, DIR = O, BUS=S_AXIS_S2MM
PORT s_axis_s2mm_tready = TREADY, DIR = I, BUS=S_AXIS_S2MM

## AXI Interface
PORT s_axi_aclk = ACLK, DIR = I, SIGIS = CLK, BUS = S_AXI
PORT s_axi_aresetn = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT s_axi_awaddr = AWADDR, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT s_axi_awvalid = AWVALID, DIR = I, BUS = S_AXI
PORT s_axi_wdata = WDATA, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT s_axi_wstrb = WSTRB, DIR = I, VEC = [3:0], ENDIAN = LITTLE, BUS = S_AXI
PORT s_axi_wvalid = WVALID, DIR = I, BUS = S_AXI
PORT s_axi_bready = BREADY, DIR = I, BUS = S_AXI
PORT s_axi_araddr = ARADDR, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT s_axi_arvalid = ARVALID, DIR = I, BUS = S_AXI
PORT s_axi_rready = RREADY, DIR = I, BUS = S_AXI
PORT s_axi_arready = ARREADY, DIR = O, BUS = S_AXI
PORT s_axi_rdata = RDATA, DIR = O, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT s_axi_rresp = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT s_axi_rvalid = RVALID, DIR = O, BUS = S_AXI
PORT s_axi_wready = WREADY, DIR = O, BUS = S_AXI
PORT s_axi_bresp = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT s_axi_bvalid = BVALID, DIR = O, BUS = S_AXI
PORT s_axi_awready = AWREADY, DIR = O, BUS = S_AXI

END
