Ngspice Users Manual
Version 26
(Describes ngspice-26 release version)

Paolo Nenzi, Holger Vogt

Locations

Status

To Do

1. Review of chapt. 1.3
2. hfet1,2 model descriptions

How to use this manual

Part I. Ngspice User Manual

Prefaces

Preface to the first edition

1. The spice3f5 manual,
2. the XSPICE user’s manual,
3. the CIDER user’s manual

Indeed. At the end of the day, this is engineering, and one learns to live
within the limitations of the tools.

Preface to the actual edition (as of January 2013)

Acknowledgments

ngspice contributors

XSPICE

1 Introduction

• CIDER: a mixed-level circuit and device simulator integrated into ngspice code. CIDER was originally the name of the mixed-level extension made to spice3f5.
• GSS: GSS (now called GENIUS) TCAD is a 2D simulator developed independently from ngspice. The device simulator itself is free and not included into ngspice, but a socket interface is provided.

1.1 Simulation Algorithms

1.1.1 Analog Simulation

1.1.2 Digital Simulation

1.1.3 Mixed-Mode Simulation

1.1.3.1 User-Defined Nodes

1.1.4 Mixed-Level Simulation

1.1.4.1 CIDER (DSIM)

1.1.4.2 GSS TCAD

1.2 Supported Analyses

1. DC Analysis (Operating Point and DC Sweep)
2. AC Small-Signal Analysis
3. Transient Analysis
4. Pole-Zero Analysis
5. Small-Signal Distortion Analysis
6. Sensitivity Analysis
7. Noise Analysis

1.2.1 DC Analyses

1.2.2 AC Small-Signal Analysis

1.2.3 Transient Analysis

1.2.4 Pole-Zero Analysis

1.2.5 Small-Signal Distortion Analysis

• Diodes (DIO),
• BJT,
• JFET (level 1),
• MOSFETs (levels 1, 2, 3, 9, and BSIM1),
• MESFET (level 1).

1.2.6 Sensitivity Analysis

1.2.7 Noise Analysis

1.2.8 Periodic Steady State Analysis

1.3 Analysis at Different Temperatures

1.4 Convergence

1. The nonlinear branch currents converge to within a tolerance of 0.1% or 1 picoamp (1.0e-12 Amp), whichever is larger.
2. The node voltages converge to within a tolerance of 0.1% or 1 microvolt (1.0e-6 Volt), whichever is larger.

1.4.1 Voltage convergence criterion

1.4.2 Current convergence criterion

1.4.3 Convergence failure

2 Circuit Description

2.1 General Structure and Conventions

2.1.1 Input file structure

• The first line in the input file must be the title, which is the only comment line that does not need any special character in the first place.
• The last line must be .end.

2.1.2 Circuit elements (device instances)

• the element instance name,
• the circuit nodes to which the element is connected,
• and the values of the parameters that determine the electrical characteristics of the element.

2.1.3 Some naming conventions

• The circuit cannot contain a loop of voltage sources and/or inductors and cannot contain a cut-set of current sources and/or capacitors.
• Each node in the circuit must have a dc path to ground.
• Every node must have at least two connections except for transmission line nodes (to permit unterminated transmission lines) and MOSFET substrate nodes (which have two internal connections anyway).

2.2 Basic lines

2.2.1 .TITLE line

POWER AMPLIFIER CIRCUIT
* additional lines following
*...
​
Test of CAM cell
* additional lines following
*...

******************************
* additional lines following
*...
.TITLE Test of CAM cell
* additional lines following
*...

Test of CAM cell
* additional lines following
*...
*TITLE Test of CAM cell
* additional lines following
*...

2.2.2 .END Line

.end

2.2.3 Comments

* <any comment>

* RF=1K Gain should be 100
* Check open-loop gain and phase margin

2.2.4 End-of-line comments

<any command> ;<any comment>
<any command> $ <any comment>

RF2=1K ;Gain should be 100
C1=10p $ Check open-loop gain and phase margin
.param n1=1 //new value

2.3  .MODEL Device Models

.model mname type(pname1=pval1 pname2=pval2 ... )

.model MOD1 npn (bf=50 is=1e-13 vbf=50)

2.4 .SUBCKT Subcircuits

Example:

* The following is the instance card: 
*
xdiv1 10 7 0 vdivide
​
* The following are the subcircuit definition cards: 
*
.subckt vdivide 1 2 3 
r1 1 2 10K 
r2 2 3 5K 
.ends

• Resistor ”R1” is connected from port “1” to port “2”, and has value 10 kOhms.
• Resistor “R2” is connected from port “2” to port “3”, and has value 5 kOhms.

2.4.1 .SUBCKT Line

.SUBCKT subnam N1 <N2 N3 ...>

.SUBCKT OPAMP 1 2 3 4

2.4.2 .ENDS Line

.ENDS <SUBNAM>

.ENDS OPAMP

2.4.3  Subcircuit Calls

XYYYYYYY N1 <N2 N3 ...> SUBNAM

X1 2 4 17 3 1 MULTI

2.5 .GLOBAL

.GLOBAL nodename

.GLOBAL gnd vcc

2.6  .INCLUDE

.INCLUDE filename

.INCLUDE /users/spice/common/bsim3-param.mod

2.7  .LIB

.LIB filename libname

.LIB /users/spice/common/mosfets.lib mos1

2.8 .PARAM Parametric netlists

2.8.1  .param line

.param <ident> = <expr>  <ident> = <expr> ....

.param pippo=5
.param po=6 pp=7.8 pap={AGAUSS(pippo, 1, 1.67)}
.param pippp={pippo + pp}
.param p={pp}
.param pop=’pp+p’

2.8.2 Brace expressions in circuit elements:

{ <expr> }

2.8.3  Subcircuit parameters

.subckt <identn> node node ...  <ident>=<value> <ident>=<value> ...

.subckt myfilter in out rval=100k cval=100nF

X<name> node node ... <identn> <ident>=<value> <ident>=<value> ...

X1 input output myfilter rval=1k cval=1n

* Param-example 
.param amplitude= 1V
*
.subckt myfilter in out rval=100k  cval=100nF 
Ra in p1   {2*rval} 
Rb p1 out  {2*rval} 
C1 p1 0    {2*cval} 
Ca in p2   {cval} 
Cb p2 out  {cval} 
R1 p2 0    {rval} 
.ends myfilter
*
X1 input output myfilter rval=1k cval=1n 
V1 input 0 AC {amplitude}
.end

2.8.4 Symbol scope

2.8.5  Syntax of expressions

​
<atom> where <atom> is either a spice number or an identifier 
<unary-operator> <atom> 
<function-name> ( <expr> [ , <expr> ...] ) 
<atom> <binary-operator> <expr> 
( <expr> )