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bladeRF HDL Change Log Summary

For more detailed information, please see the git change log and issue tracker
hosted on GitHub: https://github.com/nuand/bladeRF
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v0.0.6 (2014-07-20)
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  * Fixed FPGA correction for gain/phase

v0.0.5 (2014-06-21)
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 * Added expansion board support for XB-200


v0.0.4 (2014-05-07)
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 * Added metadata timestamp support
    - Added RX/TX metadata FIFOs
 * Added FPGA digital loopback


v0.0.3 (2014-02-01)
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 * Tweaked constraints for FX3 interface drive strength
 * Add 32-bit counter mode for RX performance testing


v0.0.2 (2014-01-14)
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 * Tweaked constraints for the FX3 interface
 * Fixed SPI/UART signal contention issue
 * Fixed phase range for IQ correction block


v0.0.1 (2013-12-28)
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 * Updated to use Quartus 13.1 tools
    - Renamed OpenCores I2C Qsys core to not conflict
 * Introduced faster UART bridge (4Mbps versus 115.2kbps)
 * Added IQ correction block
 * Added FPGA version numbering
 * Made FX3 GPIF FSM more maintainable
