The Netwide Assembler: NASM

Appendix B: Intel x86 Instruction Reference

This appendix provides a complete list of the machine instructions which NASM will assemble, and a short description of the function of each one.

It is not intended to be exhaustive documentation on the fine details of the instructions' function, such as which exceptions they can trigger: for such documentation, you should go to Intel's Web site, http://www.intel.com/.

Instead, this appendix is intended primarily to provide documentation on the way the instructions may be used within NASM. For example, looking up LOOP will tell you that NASM allows CX or ECX to be specified as an optional second argument to the LOOP instruction, to enforce which of the two possible counter registers should be used if the default is not the one desired.

The instructions are not quite listed in alphabetical order, since groups of instructions with similar functions are lumped together in the same entry. Most of them don't move very far from their alphabetic position because of this.

B.1 Key to Operand Specifications

The instruction descriptions in this appendix specify their operands using the following notation:

Registers: reg8 denotes an 8-bit general purpose register, reg16 denotes a 16-bit general purpose register, and reg32 a 32-bit one. fpureg denotes one of the eight FPU stack registers, mmxreg denotes one of the eight 64-bit MMX registers, and segreg denotes a segment register. In addition, some registers (such as AL, DX or ECX) may be specified explicitly.
Immediate operands: imm denotes a generic immediate operand. imm8, imm16 and imm32 are used when the operand is intended to be a specific size. For some of these instructions, NASM needs an explicit specifier: for example, ADD ESP,16 could be interpreted as either ADD r/m32,imm32 or ADD r/m32,imm8. NASM chooses the former by default, and so you must specify ADD ESP,BYTE 16 for the latter.
Memory references: mem denotes a generic memory reference; mem8, mem16, mem32, mem64 and mem80 are used when the operand needs to be a specific size. Again, a specifier is needed in some cases: DEC [address] is ambiguous and will be rejected by NASM. You must specify DEC BYTE [address], DEC WORD [address] or DEC DWORD [address] instead.
Restricted memory references: one form of the MOV instruction allows a memory address to be specified without allowing the normal range of register combinations and effective address processing. This is denoted by memoffs8, memoffs16 and memoffs32.
Register or memory choices: many instructions can accept either a register or a memory reference as an operand. r/m8 is a shorthand for reg8/mem8; similarly r/m16 and r/m32. r/m64 is MMX-related, and is a shorthand for mmxreg/mem64.

B.2 Key to Opcode Descriptions

This appendix also provides the opcodes which NASM will generate for each form of each instruction. The opcodes are listed in the following way:

A hex number, such as 3F, indicates a fixed byte containing that number.
A hex number followed by +r, such as C8+r, indicates that one of the operands to the instruction is a register, and the `register value' of that register should be added to the hex number to produce the generated byte. For example, EDX has register value 2, so the code C8+r, when the register operand is EDX, generates the hex byte CA. Register values for specific registers are given in section B.2.1.
A hex number followed by +cc, such as 40+cc, indicates that the instruction name has a condition code suffix, and the numeric representation of the condition code should be added to the hex number to produce the generated byte. For example, the code 40+cc, when the instruction contains the NE condition, generates the hex byte 45. Condition codes and their numeric representations are given in section B.2.2.
A slash followed by a digit, such as /2, indicates that one of the operands to the instruction is a memory address or register (denoted mem or r/m, with an optional size). This is to be encoded as an effective address, with a ModR/M byte, an optional SIB byte, and an optional displacement, and the spare (register) field of the ModR/M byte should be the digit given (which will be from 0 to 7, so it fits in three bits). The encoding of effective addresses is given in section B.2.5.
The code /r combines the above two: it indicates that one of the operands is a memory address or r/m, and another is a register, and that an effective address should be generated with the spare (register) field in the ModR/M byte being equal to the `register value' of the register operand. The encoding of effective addresses is given in section B.2.5; register values are given in section B.2.1.
The codes ib, iw and id indicate that one of the operands to the instruction is an immediate value, and that this is to be encoded as a byte, little-endian word or little-endian doubleword respectively.
The codes rb, rw and rd indicate that one of the operands to the instruction is an immediate value, and that the difference between this value and the address of the end of the instruction is to be encoded as a byte, word or doubleword respectively. Where the form rw/rd appears, it indicates that either rw or rd should be used according to whether assembly is being performed in BITS 16 or BITS 32 state respectively.
The codes ow and od indicate that one of the operands to the instruction is a reference to the contents of a memory address specified as an immediate value: this encoding is used in some forms of the MOV instruction in place of the standard effective-address mechanism. The displacement is encoded as a word or doubleword. Again, ow/od denotes that ow or od should be chosen according to the BITS setting.
The codes o16 and o32 indicate that the given form of the instruction should be assembled with operand size 16 or 32 bits. In other words, o16 indicates a 66 prefix in BITS 32 state, but generates no code in BITS 16 state; and o32 indicates a 66 prefix in BITS 16 state but generates nothing in BITS 32.
The codes a16 and a32, similarly to o16 and o32, indicate the address size of the given form of the instruction. Where this does not match the BITS setting, a 67 prefix is required.

B.2.1 Register Values

Where an instruction requires a register value, it is already implicit in the encoding of the rest of the instruction what type of register is intended: an 8-bit general-purpose register, a segment register, a debug register, an MMX register, or whatever. Therefore there is no problem with registers of different types sharing an encoding value.

The encodings for the various classes of register are:

8-bit general registers: AL is 0, CL is 1, DL is 2, BL is 3, AH is 4, CH is 5, DH is 6, and BH is 7.
16-bit general registers: AX is 0, CX is 1, DX is 2, BX is 3, SP is 4, BP is 5, SI is 6, and DI is 7.
32-bit general registers: EAX is 0, ECX is 1, EDX is 2, EBX is 3, ESP is 4, EBP is 5, ESI is 6, and EDI is 7.
Segment registers: ES is 0, CS is 1, SS is 2, DS is 3, FS is 4, and GS is 5.
Floating-point registers: ST0 is 0, ST1 is 1, ST2 is 2, ST3 is 3, ST4 is 4, ST5 is 5, ST6 is 6, and ST7 is 7.
64-bit MMX registers: MM0 is 0, MM1 is 1, MM2 is 2, MM3 is 3, MM4 is 4, MM5 is 5, MM6 is 6, and MM7 is 7.
Control registers: CR0 is 0, CR2 is 2, CR3 is 3, and CR4 is 4.
Debug registers: DR0 is 0, DR1 is 1, DR2 is 2, DR3 is 3, DR6 is 6, and DR7 is 7.
Test registers: TR3 is 3, TR4 is 4, TR5 is 5, TR6 is 6, and TR7 is 7.

(Note that wherever a register name contains a number, that number is also the register value for that register.)

B.2.2 Condition Codes

The available condition codes are given here, along with their numeric representations as part of opcodes. Many of these condition codes have synonyms, so several will be listed at a time.

In the following descriptions, the word `either', when applied to two possible trigger conditions, is used to mean `either or both'. If `either but not both' is meant, the phrase `exactly one of' is used.

O is 0 (trigger if the overflow flag is set); NO is 1.
B, C and NAE are 2 (trigger if the carry flag is set); AE, NB and NC are 3.
E and Z are 4 (trigger if the zero flag is set); NE and NZ are 5.
BE and NA are 6 (trigger if either of the carry or zero flags is set); A and NBE are 7.
S is 8 (trigger if the sign flag is set); NS is 9.
P and PE are 10 (trigger if the parity flag is set); NP and PO are 11.
L and NGE are 12 (trigger if exactly one of the sign and overflow flags is set); GE and NL are 13.
LE and NG are 14 (trigger if either the zero flag is set, or exactly one of the sign and overflow flags is set); G and NLE are 15.

Note that in all cases, the sense of a condition code may be reversed by changing the low bit of the numeric representation.

For details of when an instruction sets each of the status flags, see the individual instruction, plus the Status Flags reference in section B.2.4

B.2.3 SSE Condition Predicates

The condition predicates for SSE comparison instructions are the codes used as part of the opcode, to determine what form of comparison is being carried out. In each case, the imm8 value is the final byte of the opcode encoding, and the predicate is the code used as part of the mnemonic for the instruction (equivalent to the "cc" in an integer instruction that used a condition code). The instructions that use this will give details of what the various mnemonics are, this table is used to help you work out details of what is happening.

Predi- imm8 Description Relation where: Emula- Result if QNaN cate Encod- A Is 1st Operand tion NaN Signals ing B Is 2nd Operand Operand Invalid

EQ 000B equal A = B False No

LT 001B less-than A < B False Yes

LE 010B less-than- A <= B False Yes or-equal

--- ---- greater A > B Swap False Yes than Operands, Use LT

--- ---- greater- A >= B Swap False Yes than-or-equal Operands, Use LE

UNORD 011B unordered A, B = Unordered True No

NEQ 100B not-equal A != B True No

NLT 101B not-less- NOT(A < B) True Yes than

NLE 110B not-less- NOT(A <= B) True Yes than-or- equal

--- ---- not-greater NOT(A > B) Swap True Yes than Operands, Use NLT

--- ---- not-greater NOT(A >= B) Swap True Yes than- Operands, or-equal Use NLE

ORD 111B ordered A , B = Ordered False No

The unordered relationship is true when at least one of the two values being compared is a NaN or in an unsupported format.

Note that the comparisons which are listed as not having a predicate or encoding can only be achieved through software emulation, as described in the "emulation" column. Note in particular that an instruction such as greater-than is not the same as NLE, as, unlike with the CMP instruction, it has to take into account the possibility of one operand containing a NaN or an unsupported numeric format.

B.2.4 Status Flags

The status flags provide some information about the result of the arithmetic instructions. This information can be used by conditional instructions (such a Jcc and CMOVcc) as well as by some of the other instructions (such as ADC and INTO).

There are 6 status flags:

CF - Carry flag.

Set if an arithmetic operation generates a carry or a borrow out of the most-significant bit of the result; cleared otherwise. This flag indicates an overflow condition for unsigned-integer arithmetic. It is also used in multiple-precision arithmetic.

PF - Parity flag.

Set if the least-significant byte of the result contains an even number of 1 bits; cleared otherwise.

AF - Adjust flag.

Set if an arithmetic operation generates a carry or a borrow out of bit 3 of the result; cleared otherwise. This flag is used in binary-coded decimal (BCD) arithmetic.

ZF - Zero flag.

Set if the result is zero; cleared otherwise.

SF - Sign flag.

Set equal to the most-significant bit of the result, which is the sign bit of a signed integer. (0 indicates a positive value and 1 indicates a negative value.)

OF - Overflow flag.

Set if the integer result is too large a positive number or too small a negative number (excluding the sign-bit) to fit in the destina-tion operand; cleared otherwise. This flag indicates an overflow condition for signed-integer (two�s complement) arithmetic.

B.2.5 Effective Address Encoding: ModR/M and SIB

An effective address is encoded in up to three parts: a ModR/M byte, an optional SIB byte, and an optional byte, word or doubleword displacement field.

The ModR/M byte consists of three fields: the mod field, ranging from 0 to 3, in the upper two bits of the byte, the r/m field, ranging from 0 to 7, in the lower three bits, and the spare (register) field in the middle (bit 3 to bit 5). The spare field is not relevant to the effective address being encoded, and either contains an extension to the instruction opcode or the register value of another operand.

The ModR/M system can be used to encode a direct register reference rather than a memory access. This is always done by setting the mod field to 3 and the r/m field to the register value of the register in question (it must be a general-purpose register, and the size of the register must already be implicit in the encoding of the rest of the instruction). In this case, the SIB byte and displacement field are both absent.

In 16-bit addressing mode (either BITS 16 with no 67 prefix, or BITS 32 with a 67 prefix), the SIB byte is never used. The general rules for mod and r/m (there is an exception, given below) are:

The mod field gives the length of the displacement field: 0 means no displacement, 1 means one byte, and 2 means two bytes.
The r/m field encodes the combination of registers to be added to the displacement to give the accessed address: 0 means BX+SI, 1 means BX+DI, 2 means BP+SI, 3 means BP+DI, 4 means SI only, 5 means DI only, 6 means BP only, and 7 means BX only.

However, there is a special case:

If mod is 0 and r/m is 6, the effective address encoded is not [BP] as the above rules would suggest, but instead [disp16]: the displacement field is present and is two bytes long, and no registers are added to the displacement.

Therefore the effective address [BP] cannot be encoded as efficiently as [BX]; so if you code [BP] in a program, NASM adds a notional 8-bit zero displacement, and sets mod to 1, r/m to 6, and the one-byte displacement field to 0.

In 32-bit addressing mode (either BITS 16 with a 67 prefix, or BITS 32 with no 67 prefix) the general rules (again, there are exceptions) for mod and r/m are:

The mod field gives the length of the displacement field: 0 means no displacement, 1 means one byte, and 2 means four bytes.
If only one register is to be added to the displacement, and it is not ESP, the r/m field gives its register value, and the SIB byte is absent. If the r/m field is 4 (which would encode ESP), the SIB byte is present and gives the combination and scaling of registers to be added to the displacement.

If the SIB byte is present, it describes the combination of registers (an optional base register, and an optional index register scaled by multiplication by 1, 2, 4 or 8) to be added to the displacement. The SIB byte is divided into the scale field, in the top two bits, the index field in the next three, and the base field in the bottom three. The general rules are:

The base field encodes the register value of the base register.
The index field encodes the register value of the index register, unless it is 4, in which case no index register is used (so ESP cannot be used as an index register).
The scale field encodes the multiplier by which the index register is scaled before adding it to the base and displacement: 0 encodes a multiplier of 1, 1 encodes 2, 2 encodes 4 and 3 encodes 8.

The exceptions to the 32-bit encoding rules are:

If mod is 0 and r/m is 5, the effective address encoded is not [EBP] as the above rules would suggest, but instead [disp32]: the displacement field is present and is four bytes long, and no registers are added to the displacement.
If mod is 0, r/m is 4 (meaning the SIB byte is present) and base is 4, the effective address encoded is not [EBP+index] as the above rules would suggest, but instead [disp32+index]: the displacement field is present and is four bytes long, and there is no base register (but the index register is still processed in the normal way).

B.3 Key to Instruction Flags

Given along with each instruction in this appendix is a set of flags, denoting the type of the instruction. The types are as follows:

8086, 186, 286, 386, 486, PENT and P6 denote the lowest processor type that supports the instruction. Most instructions run on all processors above the given type; those that do not are documented. The Pentium II contains no additional instructions beyond the P6 (Pentium Pro); from the point of view of its instruction set, it can be thought of as a P6 with MMX capability.
3DNOW indicates that the instruction is a 3DNow! one, and will run on the AMD K6-2 and later processors. ATHLON extensions to the 3DNow! instruction set are documented as such.
CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.
FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).
KATMAI indicates that the instruction was introduced as part of the Katmai New Instruction set. These instructions are available on the Pentium III and later processors. Those which are not specifically SSE instructions are also available on the AMD Athlon.
MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.
PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.
SSE and SSE2 indicate that the instruction is a Streaming SIMD Extension instruction. These instructions operate on multiple values in a single operation. SSE was introduced with the Pentium III and SSE2 was introduced with the Pentium 4.
UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.
WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

These instructions are used in conjunction with the add, subtract, multiply and divide instructions to perform binary-coded decimal arithmetic in unpacked (one BCD digit per byte - easy to translate to and from ASCII, hence the instruction names) form. There are also packed BCD instructions DAA and DAS: see section B.60.

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

ADC performs integer addition: it adds its two operands together, plus the value of the carry flag, and leaves the result in its destination (first) operand. The destination operand can be a register or a memory location. The source operand can be a register, a memory location or an immediate value.

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

In the forms with an 8-bit immediate second operand and a longer first operand, the second operand is considered to be signed, and is sign-extended to the length of the first operand. In these cases, the BYTE qualifier is necessary to force NASM to generate this form of the instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

ADD performs integer addition: it adds its two operands together, and leaves the result in its destination (first) operand. The destination operand can be a register or a memory location. The source operand can be a register, a memory location or an immediate value.

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

AND performs a bitwise AND operation between its two operands (i.e. each bit of the result is 1 if and only if the corresponding bits of the two inputs were both 1), and stores the result in the destination (first) operand. The destination operand can be a register or a memory location. The source operand can be a register, a memory location or an immediate value.

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

ANDNPD inverts the bits of the two double-precision floating-point values in the destination register, and then performs a logical AND between the two double-precision floating-point values in the source operand and the temporary inverted result, storing the result in the destination register.

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

ANDNPS inverts the bits of the four single-precision floating-point values in the destination register, and then performs a logical AND between the four single-precision floating-point values in the source operand and the temporary inverted result, storing the result in the destination register.

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

KATMAI indicates that the instruction was introduced as part of the Katmai New Instruction set. These instructions are available on the Pentium III and later processors. Those which are not specifically SSE instructions are also available on the AMD Athlon.

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

SSE and SSE2 indicate that the instruction is a Streaming SIMD Extension instruction. These instructions operate on multiple values in a single operation. SSE was introduced with the Pentium III and SSE2 was introduced with the Pentium 4.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.16 `ARPL`: Adjust RPL Field of Selector

ARPL r/m16,reg16              ; 63 /r                [286,PRIV]

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (reque documented as such.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.

WILLAMETTE indicates that the instruction was introduced as part of the new instruction set in the Pentium 4 and Intel Xeon processors. These instructions are also known as SSE2 instructions.

B.4 `AAA`, `AAS`, `AAM`, `AAD`: ASCII Adjustments

AAA                           ; 37                   [8086]

AAS                           ; 3F                   [8086]

AAD                           ; D5 0A                [8086] 
AAD imm                       ; D5 ib                [8086]

AAM                           ; D4 0A                [8086] 
AAM imm                       ; D4 ib                [8086]

AAA (ASCII Adjust After Addition) should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.
AAS (ASCII Adjust AL After Subtraction) works similarly to AAA, but is for use after SUB instructions rather than ADD.
AAM (ASCII Adjust AX After Multiply) is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.
AAD (ASCII Adjust AX Before Division) performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.

B.5 `ADC`: Add with Carry

ADC r/m8,reg8                 ; 10 /r                [8086] 
ADC r/m16,reg16               ; o16 11 /r            [8086] 
ADC r/m32,reg32               ; o32 11 /r            [386]

ADC reg8,r/m8                 ; 12 /r                [8086] 
ADC reg16,r/m16               ; o16 13 /r            [8086] 
ADC reg32,r/m32               ; o32 13 /r            [386]

ADC r/m8,imm8                 ; 80 /2 ib             [8086] 
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] 
ADC r/m32,imm32               ; o32 81 /2 id         [386]

ADC r/m16,imm8                ; o16 83 /2 ib         [8086] 
ADC r/m32,imm8                ; o32 83 /2 ib         [386]

ADC AL,imm8                   ; 14 ib                [8086] 
ADC AX,imm16                  ; o16 15 iw            [8086] 
ADC EAX,imm32                 ; o32 15 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

To add two numbers without also adding the contents of the carry flag, use ADD (section B.6).

B.6 `ADD`: Add Integers

ADD r/m8,reg8                 ; 00 /r                [8086] 
ADD r/m16,reg16               ; o16 01 /r            [8086] 
ADD r/m32,reg32               ; o32 01 /r            [386]

ADD reg8,r/m8                 ; 02 /r                [8086] 
ADD reg16,r/m16               ; o16 03 /r            [8086] 
ADD reg32,r/m32               ; o32 03 /r            [386]

ADD r/m8,imm8                 ; 80 /0 ib             [8086] 
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] 
ADD r/m32,imm32               ; o32 81 /0 id         [386]

ADD r/m16,imm8                ; o16 83 /0 ib         [8086] 
ADD r/m32,imm8                ; o32 83 /0 ib         [386]

ADD AL,imm8                   ; 04 ib                [8086] 
ADD AX,imm16                  ; o16 05 iw            [8086] 
ADD EAX,imm32                 ; o32 05 id            [386]

The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

B.7 `ADDPD`: ADD Packed Double-Precision FP Values

ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]

ADDPD performs addition on each of two packed double-precision FP value pairs.

   dst[0-63]   := dst[0-63]   + src[0-63], 
   dst[64-127] := dst[64-127] + src[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.8 `ADDPS`: ADD Packed Single-Precision FP Values

ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]

ADDPS performs addition on each of four packed single-precision FP value pairs

   dst[0-31]   := dst[0-31]   + src[0-31], 
   dst[32-63]  := dst[32-63]  + src[32-63], 
   dst[64-95]  := dst[64-95]  + src[64-95], 
   dst[96-127] := dst[96-127] + src[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.9 `ADDSD`: ADD Scalar Double-Precision FP Values

ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]

ADDSD adds the low double-precision FP values from the source and destination operands and stores the double-precision FP result in the destination operand.

   dst[0-63]   := dst[0-63] + src[0-63], 
   dst[64-127) remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.

B.10 `ADDSS`: ADD Scalar Single-Precision FP Values

ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]

ADDSD adds the low single-precision FP values from the source and destination operands and stores the single-precision FP result in the destination operand.

   dst[0-31]   := dst[0-31] + src[0-31], 
   dst[32-127] remains unchanged.

The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.

B.11 `AND`: Bitwise AND

AND r/m8,reg8                 ; 20 /r                [8086] 
AND r/m16,reg16               ; o16 21 /r            [8086] 
AND r/m32,reg32               ; o32 21 /r            [386]

AND reg8,r/m8                 ; 22 /r                [8086] 
AND reg16,r/m16               ; o16 23 /r            [8086] 
AND reg32,r/m32               ; o32 23 /r            [386]

AND r/m8,imm8                 ; 80 /4 ib             [8086] 
AND r/m16,imm16               ; o16 81 /4 iw         [8086] 
AND r/m32,imm32               ; o32 81 /4 id         [386]

AND r/m16,imm8                ; o16 83 /4 ib         [8086] 
AND r/m32,imm8                ; o32 83 /4 ib         [386]

AND AL,imm8                   ; 24 ib                [8086] 
AND AX,imm16                  ; o16 25 iw            [8086] 
AND EAX,imm32                 ; o32 25 id            [386]

The MMX instruction PAND (see section B.205) performs the same operation on the 64-bit MMX registers.

B.12 `ANDNPD`: Bitwise Logical AND NOT of Packed Double-Precision FP Values

ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]

   dst[0-63]   := src[0-63]   AND NOT dst[0-63], 
   dst[64-127] := src[64-127] AND NOT dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.13 `ANDNPS`: Bitwise Logical AND NOT of Packed Single-Precision FP Values

ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]

   dst[0-31]   := src[0-31]   AND NOT dst[0-31], 
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], 
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], 
   dst[96-127] := src[96-127] AND NOT dst[96-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.14 `ANDPD`: Bitwise Logical AND For Single FP

ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]

ANDPD performs a bitwise logical AND of the two double-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-63]   := src[0-63]   AND dst[0-63], 
   dst[64-127] := src[64-127] AND dst[64-127].

The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.

B.15 `ANDPS`: Bitwise Logical AND For Single FP

ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]

ANDPS performs a bitwise logical AND of the four single-precision floating point values in the source and destination operand, and stores the result in the destination register.

   dst[0-31]   := src[0-31]   AND dst[0-31], 
   dst[32-63]  := src[32-63]  AND dst[32-63], 
   dst[64-95]  := src[64-95]  AND dst[64-95], 
   dst[96-127] := src[96-127] AND dst[96-127].

The destination