<Comment>//////////////////////////////////////////////////////////////////////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>////  OR1200's DC FSM                                             ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>////  This file is part of the OpenRISC 1200 project              ////</Comment><br/>
<Comment>////  http://opencores.org/project,or1k                           ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>////  Description                                                 ////</Comment><br/>
<Comment>////  Data cache state machine                                    ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>////  To Do:                                                      ////</Comment><br/>
<Comment>////   - Test error during line read or write                     ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>////  Author(s):                                                  ////</Comment><br/>
<Comment>////      - Damjan Lampret, lampret@opencores.org                 ////</Comment><br/>
<Comment>////      - Julius Baxter, julius@opencores.org                   ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//////////////////////////////////////////////////////////////////////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG           ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//// This source file may be used and distributed without         ////</Comment><br/>
<Comment>//// restriction provided that this copyright statement is not    ////</Comment><br/>
<Comment>//// removed from the file and that any derivative work contains  ////</Comment><br/>
<Comment>//// the original copyright notice and the associated disclaimer. ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//// This source file is free software; you can redistribute it   ////</Comment><br/>
<Comment>//// and/or modify it under the terms of the GNU Lesser General   ////</Comment><br/>
<Comment>//// Public License as published by the Free Software Foundation; ////</Comment><br/>
<Comment>//// either version 2.1 of the License, or (at your option) any   ////</Comment><br/>
<Comment>//// later version.                                               ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//// This source is distributed in the hope that it will be       ////</Comment><br/>
<Comment>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</Comment><br/>
<Comment>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</Comment><br/>
<Comment>//// PURPOSE.  See the GNU Lesser General Public License for more ////</Comment><br/>
<Comment>//// details.                                                     ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//// You should have received a copy of the GNU Lesser General    ////</Comment><br/>
<Comment>//// Public License along with this source; if not, download it   ////</Comment><br/>
<Comment>//// from http://www.opencores.org/lgpl.shtml                     ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//////////////////////////////////////////////////////////////////////</Comment><br/>
<Comment>//</Comment><br/>
<Comment>// $Log: or1200_dc_fsm.v,v $</Comment><br/>
<Comment>// Revision 2.0  2010/06/30 11:00:00  ORSoC</Comment><br/>
<Comment>// Minor update: </Comment><br/>
<Comment>// Bugs fixed. </Comment><br/>
<Comment>//</Comment><br/>
<dsNormal></dsNormal><br/>
<Comment>// synopsys translate_off</Comment><br/>
<Preprocessor>`include </Preprocessor><Prep. Lib>"timescale.v"</Prep. Lib><br/>
<Comment>// synopsys translate_on</Comment><br/>
<Preprocessor>`include </Preprocessor><Prep. Lib>"or1200_defines.v"</Prep. Lib><br/>
<dsNormal></dsNormal><br/>
<Preprocessor>`define OR1200_DCFSM_IDLE	3'd0</Preprocessor><br/>
<Preprocessor>`define OR1200_DCFSM_CLOADSTORE	3'd1</Preprocessor><br/>
<Preprocessor>`define OR1200_DCFSM_LOOP2	3'd2</Preprocessor><br/>
<Preprocessor>`define OR1200_DCFSM_LOOP3	3'd3</Preprocessor><br/>
<Preprocessor>`define OR1200_DCFSM_LOOP4	3'd4</Preprocessor><br/>
<Preprocessor>`define OR1200_DCFSM_FLUSH5	3'd5</Preprocessor><br/>
<Preprocessor>`define OR1200_DCFSM_INV6	3'd6</Preprocessor><br/>
<Preprocessor>`define OR1200_DCFSM_WAITSPRCS7	3'd7</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<dsNormal></dsNormal><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Data cache FSM for cache line of 16 bytes (4x singleword)</Comment><br/>
<Comment>//</Comment><br/>
<dsNormal></dsNormal><br/>
<Keyword>module</Keyword><Normal Text> or1200_dc_fsm</Normal Text><br/>
<Normal Text>  </Normal Text><Symbol>(</Symbol><br/>
<Normal Text>   </Normal Text><Comment>// Clock and reset</Comment><br/>
<Normal Text>   clk</Normal Text><Symbol>,</Symbol><Normal Text> rst</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// Internal i/f to top level DC</Comment><br/>
<Normal Text>   dc_en</Normal Text><Symbol>,</Symbol><Normal Text> dcqmem_cycstb_i</Normal Text><Symbol>,</Symbol><Normal Text> dcqmem_ci_i</Normal Text><Symbol>,</Symbol><Normal Text> dcqmem_we_i</Normal Text><Symbol>,</Symbol><Normal Text> dcqmem_sel_i</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>   tagcomp_miss</Normal Text><Symbol>,</Symbol><Normal Text> biudata_valid</Normal Text><Symbol>,</Symbol><Normal Text> biudata_error</Normal Text><Symbol>,</Symbol><Normal Text> lsu_addr</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>   dcram_we</Normal Text><Symbol>,</Symbol><Normal Text> biu_read</Normal Text><Symbol>,</Symbol><Normal Text> biu_write</Normal Text><Symbol>,</Symbol><Normal Text> biu_do_sel</Normal Text><Symbol>,</Symbol><Normal Text> dcram_di_sel</Normal Text><Symbol>,</Symbol><Normal Text> first_hit_ack</Normal Text><Symbol>,</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>   first_miss_ack</Normal Text><Symbol>,</Symbol><Normal Text> first_miss_err</Normal Text><Symbol>,</Symbol><Normal Text> burst</Normal Text><Symbol>,</Symbol><Normal Text> tag_we</Normal Text><Symbol>,</Symbol><Normal Text> tag_valid</Normal Text><Symbol>,</Symbol><Normal Text> dc_addr</Normal Text><Symbol>,</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>   dc_no_writethrough</Normal Text><Symbol>,</Symbol><Normal Text> tag_dirty</Normal Text><Symbol>,</Symbol><Normal Text> dirty</Normal Text><Symbol>,</Symbol><Normal Text> tag</Normal Text><Symbol>,</Symbol><Normal Text> tag_v</Normal Text><Symbol>,</Symbol><Normal Text> dc_block_flush</Normal Text><Symbol>,</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>   dc_block_writeback</Normal Text><Symbol>,</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>,</Symbol><Normal Text> mtspr_dc_done</Normal Text><Symbol>,</Symbol><Normal Text> spr_cswe</Normal Text><br/>
<Normal Text>   </Normal Text><Symbol>);</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Comment>// I/O</Comment><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text>				clk</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text>				rst</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text>				dc_en</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text>				dcqmem_cycstb_i</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text>				dcqmem_ci_i</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text>				dcqmem_we_i</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> 				dcqmem_sel_i</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text>				tagcomp_miss</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text>				biudata_valid</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text>				biudata_error</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> 			lsu_addr</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> 			dcram_we</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text>				biu_read</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text>				biu_write</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text> 				dcram_di_sel</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text> 				biu_do_sel</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text>				first_hit_ack</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text>				first_miss_ack</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text>				first_miss_err</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text>				burst</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text>				tag_we</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text> 				tag_valid</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> 			dc_addr</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text> 				dc_no_writethrough</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text> 				tag_dirty</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text> 				dirty</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DCTAG_W</Preprocessor><Symbol>-</Symbol><Integer>2</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> 		tag</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text> 				tag_v</Normal Text><Symbol>;</Symbol><Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text> 				dc_block_flush</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text> 				dc_block_writeback</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> 			spr_dat_i</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>output</Data Type><Normal Text> 				mtspr_dc_done</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>input</Data Type><Normal Text> 				spr_cswe</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Comment>// Internal wires and regs</Comment><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> 				addr_r</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> 				state</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DCLS</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> 		cnt</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> 					hitmiss_eval</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> 					store</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> 					load</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> 					cache_inhibit</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> 					cache_miss</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> 					cache_dirty_needs_writeback</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text>                                  did_early_load_ack</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> 					cache_spr_block_flush</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> 					cache_spr_block_writeback</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>reg</Data Type><Normal Text> 					cache_wb</Normal Text><Symbol>;</Symbol><Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				load_hit_ack</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				load_miss_ack</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				load_inhibit_ack</Normal Text><Symbol>;</Symbol><Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				store_hit_ack</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				store_hit_writethrough_ack</Normal Text><Symbol>;</Symbol><Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				store_miss_writethrough_ack</Normal Text><Symbol>;</Symbol><Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				store_inhibit_ack</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				store_miss_ack</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				dcram_we_after_line_load</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				dcram_we_during_line_load</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				tagram_we_end_of_loadstore_loop</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				tagram_dirty_bit_set</Normal Text><Symbol>;</Symbol><Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				writethrough</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> 				cache_inhibit_with_eval</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[(</Symbol><Preprocessor>`OR1200_DCLS</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>)-</Symbol><Integer>2</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		next_addr_word</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Comment>// Cache inhibit</Comment><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// Indicates whether cache is inhibited, during hitmiss_eval and after</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> cache_inhibit_with_eval </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>hitmiss_eval </Normal Text><Symbol>&</Symbol><Normal Text> dcqmem_ci_i</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>				    </Normal Text><Symbol>(!</Symbol><Normal Text>hitmiss_eval </Normal Text><Symbol>&</Symbol><Normal Text> cache_inhibit</Normal Text><Symbol>);</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Comment>// Generate of DCRAM write enables</Comment><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>// WE when non-writethrough, and had to wait for a line to load.</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> dcram_we_after_line_load </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP3</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>				    dcqmem_we_i </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>cache_dirty_needs_writeback </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>				     </Normal Text><Symbol>!</Symbol><Normal Text>did_early_load_ack</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>// WE when receiving the data cache line</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> dcram_we_during_line_load </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> load </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>				      biudata_valid</Normal Text><Symbol>;</Symbol><Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> dcram_we </Normal Text><Symbol>=(</Symbol><Comment>// Write when hit - make sure it is only when hit - could</Comment><br/>
<Normal Text>		     </Normal Text><Comment>// maybe be doing write through and don't want to corrupt</Comment><br/>
<Normal Text>		     </Normal Text><Comment>// cache lines corresponding to the writethrough addr_r.</Comment><br/>
<Normal Text>		     </Normal Text><Symbol>({</Symbol><Integer>4</Integer><Symbol>{</Symbol><Normal Text>store_hit_ack </Normal Text><Symbol>|</Symbol><Normal Text> store_hit_writethrough_ack</Normal Text><Symbol>}}</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>		     </Normal Text><Comment>// Write after load of line</Comment><br/>
<Normal Text>		     </Normal Text><Symbol>{</Symbol><Integer>4</Integer><Symbol>{</Symbol><Normal Text>dcram_we_after_line_load</Normal Text><Symbol>}})</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>		     dcqmem_sel_i		 </Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>		    </Normal Text><Comment>// Write during load</Comment><br/>
<Normal Text>		    </Normal Text><Symbol>{</Symbol><Integer>4</Integer><Symbol>{</Symbol><Normal Text>dcram_we_during_line_load</Normal Text><Symbol>}};</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Comment>// Tag RAM signals</Comment><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// WE to tag RAM when we finish loading a line.</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> tagram_we_end_of_loadstore_loop </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>((</Symbol><Normal Text>state</Normal Text><Symbol>==</Symbol><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>					     biudata_valid </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!(|</Symbol><Normal Text>cnt</Normal Text><Symbol>));</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Preprocessor>`ifndef OR1200_DC_WRITETHROUGH</Preprocessor><br/>
<Normal Text>   </Normal Text><Comment>// No writethrough, so mark a line dirty whenever we write to it</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> tagram_dirty_bit_set </Normal Text><Symbol>=</Symbol><Normal Text> store_hit_ack </Normal Text><Symbol>|</Symbol><Normal Text> store_miss_ack</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>// Generate done signal for MTSPR instructions that may block execution</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> mtspr_dc_done </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Comment>// Either DC disabled or we're not selected, or</Comment><br/>
<Normal Text>			  </Normal Text><Symbol>!</Symbol><Normal Text>dc_en </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>spr_cswe </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>			  </Normal Text><Comment>// Requested address not valid or writeback and !dirty</Comment><br/>
<Normal Text>			  </Normal Text><Symbol>((</Symbol><Normal Text>state</Normal Text><Symbol>==</Symbol><Preprocessor>`OR1200_DCFSM_FLUSH5</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			   </Normal Text><Symbol>(!</Symbol><Normal Text>tag_v </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>cache_spr_block_writeback </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dirty</Normal Text><Symbol>)))</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>			  </Normal Text><Comment>// Writeback or flush is finished</Comment><br/>
<Normal Text>			  </Normal Text><Symbol>((</Symbol><Normal Text>state</Normal Text><Symbol>==</Symbol><Preprocessor>`OR1200_DCFSM_LOOP3</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			   </Normal Text><Symbol>(</Symbol><Normal Text>cache_spr_block_flush </Normal Text><Symbol>|</Symbol><Normal Text> cache_spr_block_writeback</Normal Text><Symbol>))|</Symbol><br/>
<Normal Text>			  </Normal Text><Comment>// Invalidate of clean line finished</Comment><br/>
<Normal Text>			  </Normal Text><Symbol>((</Symbol><Normal Text>state</Normal Text><Symbol>==</Symbol><Preprocessor>`OR1200_DCFSM_INV6</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> cache_spr_block_flush</Normal Text><Symbol>);</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><br/>
<Preprocessor>`else</Preprocessor><br/>
<Normal Text> </Normal Text><Preprocessor>`ifdef</Preprocessor><Normal Text> OR1200_DC_NOSTACKWRITETHROUGH   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// For dirty bit setting when having writethrough but not for stack</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> tagram_dirty_bit_set </Normal Text><Symbol>=</Symbol><Normal Text> store_hit_ack </Normal Text><Symbol>|</Symbol><Normal Text> store_miss_ack</Normal Text><Symbol>;</Symbol><br/>
<Normal Text> </Normal Text><Preprocessor>`else</Preprocessor><br/>
<Normal Text>   </Normal Text><Comment>// Lines will never be dirty if always writethrough</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> tagram_dirty_bit_set </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Integer>0</Integer><Symbol>;</Symbol><br/>
<Normal Text> </Normal Text><Preprocessor>`endif</Preprocessor><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> mtspr_dc_done </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> tag_dirty </Normal Text><Symbol>=</Symbol><Normal Text> tagram_dirty_bit_set</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// WE to tag RAM</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> tag_we </Normal Text><Symbol>=</Symbol><Normal Text> tagram_we_end_of_loadstore_loop </Normal Text><Symbol>|</Symbol><Normal Text>		    </Normal Text><br/>
<Normal Text>                    tagram_dirty_bit_set </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_INV6</Preprocessor><Symbol>);</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>// Valid bit</Comment><br/>
<Normal Text>   </Normal Text><Comment>// Set valid when end of line load, or marking dirty (is still valid)</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> tag_valid </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text> tagram_we_end_of_loadstore_loop </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>(</Symbol><Normal Text>load </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>store </Normal Text><Symbol>&</Symbol><Normal Text> cache_spr_block_writeback</Normal Text><Symbol>))</Symbol><Normal Text> </Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>		      tagram_dirty_bit_set</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Comment>// BIU read and write</Comment><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> biu_read </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Comment>// Bus read request when:</Comment><br/>
<Normal Text>		     </Normal Text><Comment>// 1) Have a miss and not dirty or a load with inhibit</Comment><br/>
<Normal Text>		     </Normal Text><Symbol>((</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_CLOADSTORE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>		      </Normal Text><Symbol>(((</Symbol><Normal Text>hitmiss_eval </Normal Text><Symbol>&</Symbol><Normal Text> tagcomp_miss </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dirty </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			 </Normal Text><Symbol>!(</Symbol><Normal Text>store </Normal Text><Symbol>&</Symbol><Normal Text> writethrough</Normal Text><Symbol>))</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>(</Symbol><Normal Text>load </Normal Text><Symbol>&</Symbol><Normal Text> cache_inhibit_with_eval</Normal Text><Symbol>))</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> dcqmem_cycstb_i</Normal Text><Symbol>))</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>		     </Normal Text><Comment>// 2) In the loop and loading</Comment><br/>
<Normal Text>		     </Normal Text><Symbol>((</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> load</Normal Text><Symbol>);</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> biu_write </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Comment>// Bus write request when:</Comment><br/>
<Normal Text>		      </Normal Text><Comment>// 1) Have a miss and dirty or store with inhibit</Comment><br/>
<Normal Text>		      </Normal Text><Symbol>((</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_CLOADSTORE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>		       </Normal Text><Symbol>(((</Symbol><Normal Text>hitmiss_eval </Normal Text><Symbol>&</Symbol><Normal Text> tagcomp_miss </Normal Text><Symbol>&</Symbol><Normal Text> dirty</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			 </Normal Text><Symbol>(</Symbol><Normal Text>store </Normal Text><Symbol>&</Symbol><Normal Text> writethrough</Normal Text><Symbol>))</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>(</Symbol><Normal Text>store </Normal Text><Symbol>&</Symbol><Normal Text> cache_inhibit_with_eval</Normal Text><Symbol>))</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> dcqmem_cycstb_i</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>		      </Normal Text><Comment>// 2) In the loop and storing</Comment><br/>
<Normal Text>		      </Normal Text><Symbol>((</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> store</Normal Text><Symbol>);</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Comment>// Select for data to actual cache RAM (from LSU or BIU)</Comment><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Comment>// Data to DCRAM - from external bus when loading (from IU when store)</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> dcram_di_sel </Normal Text><Symbol>=</Symbol><Normal Text> load</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><Comment>// Data to external bus - always from IU except in case of bursting back</Comment><br/>
<Normal Text>   </Normal Text><Comment>//                        the line to memory. (1 selects DCRAM)</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> biu_do_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> store</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>// 3-bit wire for calculating next word of burst write, depending on</Comment><br/>
<Normal Text>   </Normal Text><Comment>// line size of data cache.</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> next_addr_word </Normal Text><Symbol>=</Symbol><Normal Text>  addr_r</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DCLS</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>+</Symbol><Normal Text> </Normal Text><Integer>1</Integer><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// Address to cache RAM (tag address also derived from this)   </Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> dc_addr </Normal Text><Symbol>=</Symbol><br/>
<Normal Text>		   </Normal Text><Comment>// First check if we've got a block flush or WB op</Comment><br/>
<Normal Text>		   </Normal Text><Symbol>((</Symbol><Normal Text>dc_block_flush </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>cache_spr_block_flush</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>		   </Normal Text><Symbol>(</Symbol><Normal Text>dc_block_writeback </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>cache_spr_block_writeback</Normal Text><Symbol>))</Symbol><Normal Text> </Normal Text><Symbol>?</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>		   </Normal Text><Case label>spr_dat_i :</Case label><br/>
<Normal Text>		   </Normal Text><Symbol>(</Symbol><Normal Text>state</Normal Text><Symbol>==</Symbol><Preprocessor>`OR1200_DCFSM_FLUSH5</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>?</Symbol><Normal Text> addr_r</Normal Text><Symbol>:</Symbol><br/>
<Normal Text>		    </Normal Text><Comment>// If no SPR action, then always put out address from LSU</Comment><br/>
<Normal Text>		    </Normal Text><Symbol>(</Symbol><Normal Text>state</Normal Text><Symbol>==</Symbol><Preprocessor>`OR1200_DCFSM_IDLE</Preprocessor><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text> hitmiss_eval</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>?</Symbol><Normal Text> lsu_addr </Normal Text><Symbol>:</Symbol><br/>
<Normal Text>		    </Normal Text><Comment>// Next, if in writeback loop, when ACKed must immediately</Comment><br/>
<Normal Text>		    </Normal Text><Comment>// output next word address (the RAM address takes a cycle</Comment><br/>
<Normal Text>		    </Normal Text><Comment>// to increment, but it's needed immediately for burst)</Comment><br/>
<Normal Text>		    </Normal Text><Comment>// otherwise, output our registered address.</Comment><br/>
<Normal Text>		    </Normal Text><Symbol>(</Symbol><Normal Text>state</Normal Text><Symbol>==</Symbol><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> biudata_valid </Normal Text><Symbol>&</Symbol><Normal Text> store </Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>?</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>		    </Normal Text><Symbol>{</Symbol><Normal Text>addr_r</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Preprocessor>`OR1200_DCLS</Preprocessor><Symbol>],</Symbol><Normal Text> next_addr_word</Normal Text><Symbol>,</Symbol><Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>}</Symbol><Normal Text> </Normal Text><Symbol>:</Symbol><Normal Text> addr_r</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Preprocessor>`ifdef OR1200_DC_WRITETHROUGH</Preprocessor><br/>
<Normal Text> </Normal Text><Preprocessor>`ifdef</Preprocessor><Normal Text> OR1200_DC_NOSTACKWRITETHROUGH   </Normal Text><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> writethrough </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dc_no_writethrough</Normal Text><Symbol>;</Symbol><br/>
<Normal Text> </Normal Text><Preprocessor>`else</Preprocessor><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> writethrough </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Integer>1</Integer><Symbol>;</Symbol><br/>
<Normal Text> </Normal Text><Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`else</Preprocessor><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> writethrough </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Integer>0</Integer><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Comment>// ACK generation for LSU</Comment><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// ACK for when it's a cache hit</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> first_hit_ack </Normal Text><Symbol>=</Symbol><Normal Text> load_hit_ack </Normal Text><Symbol>|</Symbol><Normal Text> store_hit_ack </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			  store_hit_writethrough_ack </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			  store_miss_writethrough_ack </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>			  store_inhibit_ack </Normal Text><Symbol>|</Symbol><Normal Text> store_miss_ack </Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>// ACK for when it's a cache miss - load only, is used in MUX for data back</Comment><br/>
<Normal Text>   </Normal Text><Comment>//                                  LSU straight off external data bus. In</Comment><br/>
<Normal Text>   </Normal Text><Comment>//                                  this was is also used for cache inhibit</Comment><br/>
<Normal Text>   </Normal Text><Comment>//                                  loads.</Comment><br/>
<Normal Text>   </Normal Text><Comment>// first_hit_ack takes precedence over first_miss_ack</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> first_miss_ack </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>first_hit_ack </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>load_miss_ack </Normal Text><Symbol>|</Symbol><Normal Text> load_inhibit_ack</Normal Text><Symbol>);</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// ACK cache hit on load</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> load_hit_ack </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_CLOADSTORE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			 hitmiss_eval </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>tagcomp_miss </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dcqmem_ci_i </Normal Text><Symbol>&</Symbol><Normal Text> load</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// ACK cache hit on store, no writethrough</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> store_hit_ack </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_CLOADSTORE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			  hitmiss_eval  </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>tagcomp_miss </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dcqmem_ci_i </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>			  store </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>writethrough</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// ACK cache hit on store with writethrough</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> store_hit_writethrough_ack </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_CLOADSTORE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>				       </Normal Text><Symbol>!</Symbol><Normal Text>cache_miss </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>cache_inhibit </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>				       store </Normal Text><Symbol>&</Symbol><Normal Text> writethrough </Normal Text><Symbol>&</Symbol><Normal Text> biudata_valid</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// ACK cache miss on store with writethrough</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> store_miss_writethrough_ack </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_CLOADSTORE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>					cache_miss </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>cache_inhibit </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>					store </Normal Text><Symbol>&</Symbol><Normal Text> writethrough </Normal Text><Symbol>&</Symbol><Normal Text> biudata_valid</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>      </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// ACK store when cacheinhibit</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> store_inhibit_ack </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_CLOADSTORE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>			      store </Normal Text><Symbol>&</Symbol><Normal Text> cache_inhibit </Normal Text><Symbol>&</Symbol><Normal Text> biudata_valid</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// Get the _early_ ack on first ACK back from wishbone during load only</Comment><br/>
<Normal Text>   </Normal Text><Comment>// Condition is that we're in the loop - that it's the first ack we get (can</Comment><br/>
<Normal Text>   </Normal Text><Comment>// tell from value of cnt), and we're loading a line to read from it (not</Comment><br/>
<Normal Text>   </Normal Text><Comment>// loading to write to it, in the case of a write without writethrough.)</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> load_miss_ack </Normal Text><Symbol>=</Symbol><Normal Text>  </Normal Text><Symbol>((</Symbol><Normal Text>state</Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> load </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>			    </Normal Text><Symbol>(</Symbol><Normal Text>cnt</Normal Text><Symbol>==((</Symbol><Integer>1</Integer><Normal Text> </Normal Text><Symbol><<</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCLS</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>-</Symbol><Normal Text> </Normal Text><Integer>4</Integer><Symbol>))</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> biudata_valid </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			    </Normal Text><Symbol>!(</Symbol><Normal Text>dcqmem_we_i </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>writethrough</Normal Text><Symbol>));</Symbol><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> load_inhibit_ack </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_CLOADSTORE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>			     load </Normal Text><Symbol>&</Symbol><Normal Text> cache_inhibit </Normal Text><Symbol>&</Symbol><Normal Text> biudata_valid</Normal Text><Symbol>;</Symbol><Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><br/>
<Normal Text>   </Normal Text><Comment>// This will be case of write through disabled, and had to load a line.</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> store_miss_ack </Normal Text><Symbol>=</Symbol><Normal Text> dcram_we_after_line_load</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>            </Normal Text><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> first_miss_err </Normal Text><Symbol>=</Symbol><Normal Text> biudata_error </Normal Text><Symbol>&</Symbol><Normal Text> dcqmem_cycstb_i</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>// Signal burst when in the load/store loop. We will always try to burst.</Comment><br/>
<Normal Text>   </Normal Text><Keyword>assign</Keyword><Normal Text> burst </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Symbol>);</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Comment>// Main DC FSM</Comment><br/>
<Normal Text>   </Normal Text><Comment>//</Comment><br/>
<Normal Text>   </Normal Text><Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>      </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	 state </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Preprocessor>`OR1200_DCFSM_IDLE</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>	 addr_r </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Decimal>32'd0</Decimal><Symbol>;</Symbol><br/>
<Normal Text>	 hitmiss_eval </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	 store </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	 load </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	 cnt </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Preprocessor>`OR1200_DCLS</Preprocessor><Decimal>'d0</Decimal><Symbol>;</Symbol><br/>
<Normal Text>         cache_miss </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	 cache_dirty_needs_writeback </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	 cache_inhibit </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	 did_early_load_ack </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	 cache_spr_block_flush </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	 cache_spr_block_writeback </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>      </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>      </Normal Text><Keyword>else</Keyword><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>state</Normal Text><Symbol>)</Symbol><Normal Text>	</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>	  </Normal Text><br/>
<Normal Text>          </Normal Text><Preprocessor>`OR1200_DCFSM_IDLE</Preprocessor><Normal Text> </Normal Text><Symbol>:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	     </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dc_en </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dc_block_flush </Normal Text><Symbol>|</Symbol><Normal Text> dc_block_writeback</Normal Text><Symbol>))</Symbol><br/>
<Normal Text>	       </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		  cache_spr_block_flush </Normal Text><Symbol><=</Symbol><Normal Text> dc_block_flush</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		  cache_spr_block_writeback </Normal Text><Symbol><=</Symbol><Normal Text> dc_block_writeback</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		  hitmiss_eval </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		  state </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_FLUSH5</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>		  addr_r </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	       </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	     </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dc_en </Normal Text><Symbol>&</Symbol><Normal Text> dcqmem_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	       </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		  state </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_CLOADSTORE</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>		  hitmiss_eval </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		  store </Normal Text><Symbol><=</Symbol><Normal Text>  dcqmem_we_i</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		  load </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>!</Symbol><Normal Text>dcqmem_we_i</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	       </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	     </Normal Text><br/>
<Normal Text>	     </Normal Text><br/>
<Normal Text>          </Normal Text><Keyword>end</Keyword><Normal Text> </Normal Text><Comment>// case: `OR1200_DCFSM_IDLE</Comment><br/>
<Normal Text>	  </Normal Text><br/>
<Normal Text>          </Normal Text><Preprocessor>`OR1200_DCFSM_CLOADSTORE</Preprocessor><Symbol>:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	     hitmiss_eval </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	     </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>hitmiss_eval</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>                cache_inhibit </Normal Text><Symbol><=</Symbol><Normal Text>  dcqmem_ci_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Check for cache inhibit here</Comment><br/>
<Normal Text>                cache_miss </Normal Text><Symbol><=</Symbol><Normal Text>  tagcomp_miss</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		cache_dirty_needs_writeback </Normal Text><Symbol><=</Symbol><Normal Text> dirty</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		addr_r </Normal Text><Symbol><=</Symbol><Normal Text>  lsu_addr</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>             </Normal Text><Keyword>end</Keyword><br/>
<dsNormal></dsNormal><br/>
<Normal Text>	     </Normal Text><Comment>// Evaluate any cache line load/stores in first cycle:</Comment><br/>
<Normal Text>			     </Normal Text><Comment>//</Comment><br/>
<Normal Text>	     </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>hitmiss_eval </Normal Text><Symbol>&</Symbol><Normal Text> tagcomp_miss </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!(</Symbol><Normal Text>store </Normal Text><Symbol>&</Symbol><Normal Text> writethrough</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>		 </Normal Text><Symbol>!</Symbol><Normal Text>dcqmem_ci_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	       </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		  </Normal Text><Comment>// Miss - first either:</Comment><br/>
<Normal Text>		  </Normal Text><Comment>//  1) write back dirty line </Comment><br/>
<Normal Text>		  </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dirty</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		     </Normal Text><Comment>// Address for writeback</Comment><br/>
<Normal Text>		     addr_r </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>{</Symbol><Normal Text>tag</Normal Text><Symbol>,</Symbol><Normal Text> lsu_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DCINDXH</Preprocessor><Symbol>:</Symbol><Integer>2</Integer><Symbol>],</Symbol><Decimal>2'd0</Decimal><Symbol>};</Symbol><br/>
<Normal Text>		     load </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		     store </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Preprocessor>`ifdef OR1200_VERBOSE		     </Preprocessor><br/>
<Normal Text>		     </Normal Text><System Task>$display</System Task><Symbol>(</Symbol><String>"%t: dcache miss and dirty"</String><Symbol>,</Symbol><Normal Text> </Normal Text><System Task>$time</System Task><Symbol>);</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Normal Text>		  </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>		  </Normal Text><Comment>//  2) load requested line</Comment><br/>
<Normal Text>		  </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		     addr_r </Normal Text><Symbol><=</Symbol><Normal Text>  lsu_addr</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		     load </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		     store </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		  </Normal Text><Keyword>end</Keyword><Normal Text> </Normal Text><Comment>// else: !if(dirty)</Comment><br/>
<Normal Text>		  state </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Symbol>;</Symbol><Normal Text>		  </Normal Text><br/>
<Normal Text>		  </Normal Text><Comment>// Set the counter for the burst accesses</Comment><br/>
<Normal Text>		  cnt </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>((</Symbol><Integer>1</Integer><Normal Text> </Normal Text><Symbol><<</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCLS</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>-</Symbol><Normal Text> </Normal Text><Integer>4</Integer><Symbol>);</Symbol><br/>
<Normal Text>	       </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>             </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Comment>// Strobe goes low</Comment><br/>
<Normal Text>		      </Normal Text><Symbol>!</Symbol><Normal Text>dcqmem_cycstb_i </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>		      </Normal Text><Comment>// Cycle finishes</Comment><br/>
<Normal Text>		      </Normal Text><Symbol>(!</Symbol><Normal Text>hitmiss_eval </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>biudata_valid </Normal Text><Symbol>|</Symbol><Normal Text> biudata_error</Normal Text><Symbol>))</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><br/>
<Normal Text>		      </Normal Text><Comment>// Cache hit in first cycle....</Comment><br/>
<Normal Text>		      </Normal Text><Symbol>(</Symbol><Normal Text>hitmiss_eval </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>tagcomp_miss </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dcqmem_ci_i </Normal Text><Symbol>&</Symbol><br/>
<Normal Text>		      </Normal Text><Comment>// .. and you're not doing a writethrough store..</Comment><br/>
<Normal Text>		      </Normal Text><Symbol>!(</Symbol><Normal Text>store </Normal Text><Symbol>&</Symbol><Normal Text> writethrough</Normal Text><Symbol>)))</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>                state </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Preprocessor>`OR1200_DCFSM_IDLE</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>                load </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		store </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		cache_inhibit </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		cache_dirty_needs_writeback </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>             </Normal Text><Keyword>end</Keyword><Normal Text>	     </Normal Text><br/>
<Normal Text>          </Normal Text><Keyword>end</Keyword><Normal Text> </Normal Text><Comment>// case: `OR1200_DCFSM_CLOADSTORE	  </Comment><br/>
<Normal Text>	  </Normal Text><br/>
<Normal Text>          </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Normal Text> </Normal Text><Symbol>:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><Normal Text> </Normal Text><Comment>// loop/abort	     </Comment><br/>
<Normal Text>             </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>dc_en</Normal Text><Symbol>|</Symbol><Normal Text> biudata_error</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>                state </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Preprocessor>`OR1200_DCFSM_IDLE</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>                load </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		store </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		cnt </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCLS</Preprocessor><Decimal>'d0</Decimal><Symbol>;</Symbol><br/>
<Normal Text>             </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>             </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>biudata_valid </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>(|</Symbol><Normal Text>cnt</Normal Text><Symbol>))</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>                cnt </Normal Text><Symbol><=</Symbol><Normal Text>  cnt </Normal Text><Symbol>-</Symbol><Normal Text> </Normal Text><Integer>4</Integer><Symbol>;</Symbol><br/>
<Normal Text>                addr_r</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DCLS</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><Normal Text>  addr_r</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DCLS</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>+</Symbol><Normal Text> </Normal Text><Integer>1</Integer><Symbol>;</Symbol><br/>
<Normal Text>             </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	     </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>biudata_valid </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!(|</Symbol><Normal Text>cnt</Normal Text><Symbol>))</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		state </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP3</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>		addr_r </Normal Text><Symbol><=</Symbol><Normal Text>  lsu_addr</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		load </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		store </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	     </Normal Text><Keyword>end</Keyword><br/>
<dsNormal></dsNormal><br/>
<Normal Text>	     </Normal Text><Comment>// Track if we did an early ack during a load</Comment><br/>
<Normal Text>	     </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>load_miss_ack</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	       did_early_load_ack </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>	     </Normal Text><br/>
<dsNormal></dsNormal><br/>
<Normal Text>          </Normal Text><Keyword>end</Keyword><Normal Text> </Normal Text><Comment>// case: `OR1200_DCFSM_LOOP2</Comment><br/>
<Normal Text>	  </Normal Text><br/>
<Normal Text>	  </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP3</Preprocessor><Symbol>:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><Normal Text> </Normal Text><Comment>// figure out next step</Comment><br/>
<Normal Text>	     </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>cache_dirty_needs_writeback</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		</Normal Text><Comment>// Just did store of the dirty line so now load new one</Comment><br/>
<Normal Text>		load </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Comment>// Set the counter for the burst accesses</Comment><br/>
<Normal Text>		cnt </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>((</Symbol><Integer>1</Integer><Normal Text> </Normal Text><Symbol><<</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCLS</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>-</Symbol><Normal Text> </Normal Text><Integer>4</Integer><Symbol>);</Symbol><br/>
<Normal Text>		</Normal Text><Comment>// Address of line to be loaded</Comment><br/>
<Normal Text>		addr_r </Normal Text><Symbol><=</Symbol><Normal Text>  lsu_addr</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		cache_dirty_needs_writeback </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		state </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>	     </Normal Text><Keyword>end</Keyword><Normal Text> </Normal Text><Comment>// if (cache_dirty_needs_writeback)</Comment><br/>
<Normal Text>	     </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>cache_spr_block_flush </Normal Text><Symbol>|</Symbol><Normal Text> cache_spr_block_writeback</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		</Normal Text><Comment>// Just wrote back the line to memory, we're finished.</Comment><br/>
<Normal Text>		cache_spr_block_flush </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		cache_spr_block_writeback </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		state </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_WAITSPRCS7</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>	     </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	     </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		</Normal Text><Comment>// Just loaded a new line, finish up</Comment><br/>
<Normal Text>		did_early_load_ack </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		state </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP4</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>	     </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	  </Normal Text><Keyword>end</Keyword><Normal Text> </Normal Text><Comment>// case: `OR1200_DCFSM_LOOP3</Comment><br/>
<dsNormal></dsNormal><br/>
<Normal Text>	  </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP4</Preprocessor><Symbol>:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	     state </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Preprocessor>`OR1200_DCFSM_IDLE</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>	  </Normal Text><Keyword>end</Keyword><br/>
<dsNormal></dsNormal><br/>
<Normal Text>	  </Normal Text><Preprocessor>`OR1200_DCFSM_FLUSH5</Preprocessor><Symbol>:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	     hitmiss_eval </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	     </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>hitmiss_eval </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>tag_v</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	       </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		  </Normal Text><Comment>// Not even cached, just ignore</Comment><br/>
<Normal Text>		  cache_spr_block_flush </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		  cache_spr_block_writeback </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		  state </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Preprocessor>`OR1200_DCFSM_WAITSPRCS7</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>	       </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	     </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>hitmiss_eval </Normal Text><Symbol>&</Symbol><Normal Text> tag_v</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	       </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		  </Normal Text><Comment>// Tag is valid - what do we do?</Comment><br/>
<Normal Text>		  </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>((</Symbol><Normal Text>cache_spr_block_flush </Normal Text><Symbol>|</Symbol><Normal Text> cache_spr_block_writeback</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>		      dirty</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		     </Normal Text><Comment>// Need to writeback</Comment><br/>
<Normal Text>		     </Normal Text><Comment>// Address for writeback (spr_dat_i has already changed so</Comment><br/>
<Normal Text>		     </Normal Text><Comment>// use line number from addr_r)</Comment><br/>
<Normal Text>		     addr_r </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>{</Symbol><Normal Text>tag</Normal Text><Symbol>,</Symbol><Normal Text> addr_r</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DCINDXH</Preprocessor><Symbol>:</Symbol><Integer>2</Integer><Symbol>],</Symbol><Decimal>2'd0</Decimal><Symbol>};</Symbol><br/>
<Normal Text>		     load </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		     store </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Preprocessor>`ifdef OR1200_VERBOSE		     </Preprocessor><br/>
<Normal Text>		     </Normal Text><System Task>$display</System Task><Symbol>(</Symbol><String>"%t: block flush: dirty block"</String><Symbol>,</Symbol><Normal Text> </Normal Text><System Task>$time</System Task><Symbol>);</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Normal Text>		     state </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCFSM_LOOP2</Preprocessor><Symbol>;</Symbol><Normal Text>		  </Normal Text><br/>
<Normal Text>		     </Normal Text><Comment>// Set the counter for the burst accesses</Comment><br/>
<Normal Text>		     cnt </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>((</Symbol><Integer>1</Integer><Normal Text> </Normal Text><Symbol><<</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DCLS</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>-</Symbol><Normal Text> </Normal Text><Integer>4</Integer><Symbol>);</Symbol><br/>
<Normal Text>		  </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>		  </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>cache_spr_block_flush </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dirty</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		    </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		       </Normal Text><Comment>// Line not dirty, just need to invalidate</Comment><br/>
<Normal Text>		       state </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Preprocessor>`OR1200_DCFSM_INV6</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>		    </Normal Text><Keyword>end</Keyword><Normal Text> </Normal Text><Comment>// else: !if(dirty)</Comment><br/>
<Normal Text>		  </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>cache_spr_block_writeback </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dirty</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		    </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		       </Normal Text><Comment>// Nothing to do - line is valid but not dirty</Comment><br/>
<Normal Text>		       cache_spr_block_writeback </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		       state </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Preprocessor>`OR1200_DCFSM_WAITSPRCS7</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>		    </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	  </Normal Text><Keyword>end</Keyword><Normal Text> </Normal Text><Comment>// if (hitmiss_eval & tag_v)</Comment><br/>
<Normal Text>	  </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	  </Normal Text><Preprocessor>`OR1200_DCFSM_INV6</Preprocessor><Symbol>:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	     cache_spr_block_flush </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	     </Normal Text><Comment>// Wait until SPR CS goes low before going back to idle</Comment><br/>
<Normal Text>	     </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>spr_cswe</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	       state </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Preprocessor>`OR1200_DCFSM_IDLE</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>	  </Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	  </Normal Text><Preprocessor>`OR1200_DCFSM_WAITSPRCS7</Preprocessor><Symbol>:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	     </Normal Text><Comment>// Wait until SPR CS goes low before going back to idle</Comment><br/>
<Normal Text>	     </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>spr_cswe</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	       state </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Preprocessor>`OR1200_DCFSM_IDLE</Preprocessor><Symbol>;</Symbol><br/>
<Normal Text>	  </Normal Text><Keyword>end</Keyword><br/>
<dsNormal></dsNormal><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><Normal Text> </Normal Text><Comment>// case (state)</Comment><br/>
<Normal Text>      </Normal Text><br/>
<Normal Text>   </Normal Text><Keyword>end</Keyword><Normal Text> </Normal Text><Comment>// always @ (posedge clk or `OR1200_RST_EVENT rst)</Comment><br/>
<Normal Text>   </Normal Text><br/>
<dsNormal></dsNormal><br/>
<Keyword>endmodule</Keyword><br/>
