<Comment>//////////////////////////////////////////////////////////////////////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>////  OR1200's Debug Unit                                         ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>////  This file is part of the OpenRISC 1200 project              ////</Comment><br/>
<Comment>////  http://www.opencores.org/project,or1k                       ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>////  Description                                                 ////</Comment><br/>
<Comment>////  Basic OR1200 debug unit.                                    ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>////  To Do:                                                      ////</Comment><br/>
<Comment>////   - make it smaller and faster                               ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>////  Author(s):                                                  ////</Comment><br/>
<Comment>////      - Damjan Lampret, lampret@opencores.org                 ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//////////////////////////////////////////////////////////////////////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//// This source file may be used and distributed without         ////</Comment><br/>
<Comment>//// restriction provided that this copyright statement is not    ////</Comment><br/>
<Comment>//// removed from the file and that any derivative work contains  ////</Comment><br/>
<Comment>//// the original copyright notice and the associated disclaimer. ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//// This source file is free software; you can redistribute it   ////</Comment><br/>
<Comment>//// and/or modify it under the terms of the GNU Lesser General   ////</Comment><br/>
<Comment>//// Public License as published by the Free Software Foundation; ////</Comment><br/>
<Comment>//// either version 2.1 of the License, or (at your option) any   ////</Comment><br/>
<Comment>//// later version.                                               ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//// This source is distributed in the hope that it will be       ////</Comment><br/>
<Comment>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</Comment><br/>
<Comment>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</Comment><br/>
<Comment>//// PURPOSE.  See the GNU Lesser General Public License for more ////</Comment><br/>
<Comment>//// details.                                                     ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//// You should have received a copy of the GNU Lesser General    ////</Comment><br/>
<Comment>//// Public License along with this source; if not, download it   ////</Comment><br/>
<Comment>//// from http://www.opencores.org/lgpl.shtml                     ////</Comment><br/>
<Comment>////                                                              ////</Comment><br/>
<Comment>//////////////////////////////////////////////////////////////////////</Comment><br/>
<Comment>//</Comment><br/>
<Comment>//</Comment><br/>
<Comment>// $Log: or1200_du.v,v $</Comment><br/>
<Comment>// Revision 2.0  2010/06/30 11:00:00  ORSoC</Comment><br/>
<Comment>// Minor update: </Comment><br/>
<Comment>// Bugs fixed. </Comment><br/>
<dsNormal></dsNormal><br/>
<Comment>// synopsys translate_off</Comment><br/>
<Preprocessor>`include </Preprocessor><Prep. Lib>"timescale.v"</Prep. Lib><br/>
<Comment>// synopsys translate_on</Comment><br/>
<Preprocessor>`include </Preprocessor><Prep. Lib>"or1200_defines.v"</Prep. Lib><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug unit</Comment><br/>
<Comment>//</Comment><br/>
<dsNormal></dsNormal><br/>
<Keyword>module</Keyword><Normal Text> or1200_du</Normal Text><Symbol>(</Symbol><br/>
<Normal Text>	</Normal Text><Comment>// RISC Internal Interface</Comment><br/>
<Normal Text>	clk</Normal Text><Symbol>,</Symbol><Normal Text> rst</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>	dcpu_cycstb_i</Normal Text><Symbol>,</Symbol><Normal Text> dcpu_we_i</Normal Text><Symbol>,</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>,</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>	dcpu_dat_dc</Normal Text><Symbol>,</Symbol><Normal Text> icpu_cycstb_i</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>	ex_freeze</Normal Text><Symbol>,</Symbol><Normal Text> branch_op</Normal Text><Symbol>,</Symbol><Normal Text> ex_insn</Normal Text><Symbol>,</Symbol><Normal Text> id_pc</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>	spr_dat_npc</Normal Text><Symbol>,</Symbol><Normal Text> rf_dataw</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>	du_dsr</Normal Text><Symbol>,</Symbol><Normal Text> du_dmr1</Normal Text><Symbol>,</Symbol><Normal Text> du_stall</Normal Text><Symbol>,</Symbol><Normal Text> du_addr</Normal Text><Symbol>,</Symbol><Normal Text> du_dat_i</Normal Text><Symbol>,</Symbol><Normal Text> du_dat_o</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>	du_read</Normal Text><Symbol>,</Symbol><Normal Text> du_write</Normal Text><Symbol>,</Symbol><Normal Text> du_except_stop</Normal Text><Symbol>,</Symbol><Normal Text> du_hwbkpt</Normal Text><Symbol>,</Symbol><Normal Text> du_flush_pipe</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>	spr_cs</Normal Text><Symbol>,</Symbol><Normal Text> spr_write</Normal Text><Symbol>,</Symbol><Normal Text> spr_addr</Normal Text><Symbol>,</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>,</Symbol><Normal Text> spr_dat_o</Normal Text><Symbol>,</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>	</Normal Text><Comment>// External Debug Interface</Comment><br/>
<Normal Text>	dbg_stall_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_ewt_i</Normal Text><Symbol>,</Symbol><Normal Text>	dbg_lss_o</Normal Text><Symbol>,</Symbol><Normal Text> dbg_is_o</Normal Text><Symbol>,</Symbol><Normal Text> dbg_wp_o</Normal Text><Symbol>,</Symbol><Normal Text> dbg_bp_o</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>	dbg_stb_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_we_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_adr_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_dat_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_dat_o</Normal Text><Symbol>,</Symbol><Normal Text> dbg_ack_o</Normal Text><br/>
<Symbol>);</Symbol><br/>
<dsNormal></dsNormal><br/>
<Data Type>parameter</Data Type><Normal Text> dw </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_OPERAND_WIDTH</Preprocessor><Symbol>;</Symbol><br/>
<Data Type>parameter</Data Type><Normal Text> aw </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_OPERAND_WIDTH</Preprocessor><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// I/O</Comment><br/>
<Comment>//</Comment><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// RISC Internal Interface</Comment><br/>
<Comment>//</Comment><br/>
<Data Type>input</Data Type><Normal Text>				clk</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// Clock</Comment><br/>
<Data Type>input</Data Type><Normal Text>				rst</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// Reset</Comment><br/>
<Data Type>input</Data Type><Normal Text>				dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// LSU status</Comment><br/>
<Data Type>input</Data Type><Normal Text>				dcpu_we_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// LSU status</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// LSU addr</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// LSU store data</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// LSU load data</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_FETCHOP_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>	icpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// IFETCH unit status</Comment><br/>
<Data Type>input</Data Type><Normal Text>				ex_freeze</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// EX stage freeze</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_BRANCHOP_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>	branch_op</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Branch op</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		ex_insn</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// EX insn</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			id_pc</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			spr_dat_npc</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Next PC (for trace)</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			rf_dataw</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// ALU result (for trace)</Comment><br/>
<Data Type>output</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>     du_dsr</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// DSR</Comment><br/>
<Data Type>output</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>24</Integer><Symbol>:</Symbol><Normal Text> </Normal Text><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			du_dmr1</Normal Text><Symbol>;</Symbol><br/>
<Data Type>output</Data Type><Normal Text>				du_stall</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Debug Unit Stall</Comment><br/>
<Data Type>output</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>aw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		du_addr</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Debug Unit Address</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		du_dat_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Debug Unit Data In</Comment><br/>
<Data Type>output</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		du_dat_o</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Debug Unit Data Out</Comment><br/>
<Data Type>output</Data Type><Normal Text>				du_read</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Debug Unit Read Enable</Comment><br/>
<Data Type>output</Data Type><Normal Text>				du_write</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Debug Unit Write Enable</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>13</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			du_except_stop</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Exception masked by DSR</Comment><br/>
<Data Type>output</Data Type><Normal Text>				du_hwbkpt</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Cause trap exception (HW Breakpoints)</Comment><br/>
<Data Type>output</Data Type><Normal Text>				du_flush_pipe</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Cause pipeline flush and pc<-npc</Comment><br/>
<Data Type>input</Data Type><Normal Text>				spr_cs</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// SPR Chip Select</Comment><br/>
<Data Type>input</Data Type><Normal Text>				spr_write</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// SPR Read/Write</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>aw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		spr_addr</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// SPR Address</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		spr_dat_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// SPR Data Input</Comment><br/>
<Data Type>output</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		spr_dat_o</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// SPR Data Output</Comment><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// External Debug Interface</Comment><br/>
<Comment>//</Comment><br/>
<Data Type>input</Data Type><Normal Text>			dbg_stall_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// External Stall Input</Comment><br/>
<Data Type>input</Data Type><Normal Text>			dbg_ewt_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// External Watchpoint Trigger Input</Comment><br/>
<Data Type>output</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		dbg_lss_o</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// External Load/Store Unit Status</Comment><br/>
<Data Type>output</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		dbg_is_o</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// External Insn Fetch Status</Comment><br/>
<Data Type>output</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>		dbg_wp_o</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Watchpoints Outputs</Comment><br/>
<Data Type>output</Data Type><Normal Text>			dbg_bp_o</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Breakpoint Output</Comment><br/>
<Data Type>input</Data Type><Normal Text>			dbg_stb_i</Normal Text><Symbol>;</Symbol><Normal Text>      </Normal Text><Comment>// External Address/Data Strobe</Comment><br/>
<Data Type>input</Data Type><Normal Text>			dbg_we_i</Normal Text><Symbol>;</Symbol><Normal Text>       </Normal Text><Comment>// External Write Enable</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>aw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>	dbg_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// External Address Input</Comment><br/>
<Data Type>input</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>	dbg_dat_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// External Data Input</Comment><br/>
<Data Type>output</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>	dbg_dat_o</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// External Data Output</Comment><br/>
<Data Type>output</Data Type><Normal Text>			dbg_ack_o</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// External Data Acknowledge (not WB compatible)</Comment><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>	dbg_dat_o</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// External Data Output</Comment><br/>
<Data Type>reg</Data Type><Normal Text>			dbg_ack_o</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// External Data Acknowledge (not WB compatible)</Comment><br/>
<dsNormal></dsNormal><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Some connections go directly from the CPU through DU to Debug I/F</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_STATUS_UNIMPLEMENTED</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dbg_lss_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>4'b0000</Binary><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dbg_is_o</Normal Text><Symbol>;</Symbol><br/>
<Comment>//</Comment><br/>
<Comment>// Show insn activity (temp, must be removed)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dbg_is_o </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>2'b00</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>ex_freeze </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~((</Symbol><Normal Text>ex_insn</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>26</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_OR32_NOP</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> ex_insn</Normal Text><Symbol>[</Symbol><Integer>16</Integer><Symbol>]))</Symbol><br/>
<Normal Text>		dbg_is_o </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>~</Symbol><Normal Text>dbg_is_o</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`ifdef UNUSED</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dbg_is_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dbg_lss_o </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i </Normal Text><Symbol>?</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Normal Text>dcpu_we_i</Normal Text><Symbol>,</Symbol><Normal Text> </Normal Text><Binary>3'b000</Binary><Symbol>}</Symbol><Normal Text> </Normal Text><Symbol>:</Symbol><Normal Text> </Normal Text><Binary>4'b0000</Binary><Symbol>;</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> dbg_is_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>,</Symbol><Normal Text> icpu_cycstb_i</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dbg_wp_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>11'b000_0000_0000</Binary><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Some connections go directly from Debug I/F through DU to the CPU</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>assign</Keyword><Normal Text> du_stall </Normal Text><Symbol>=</Symbol><Normal Text> dbg_stall_i</Normal Text><Symbol>;</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> du_addr </Normal Text><Symbol>=</Symbol><Normal Text> dbg_adr_i</Normal Text><Symbol>;</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> du_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dbg_dat_i</Normal Text><Symbol>;</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> du_read </Normal Text><Symbol>=</Symbol><Normal Text> dbg_stb_i </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dbg_we_i</Normal Text><Symbol>;</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> du_write </Normal Text><Symbol>=</Symbol><Normal Text> dbg_stb_i </Normal Text><Symbol>&&</Symbol><Normal Text> dbg_we_i</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// After a sw breakpoint, the replaced instruction need to be executed.</Comment><br/>
<Comment>// We flush the entire pipeline and set the pc to the current address</Comment><br/>
<Comment>// to execute the restored address.</Comment><br/>
<Comment>//</Comment><br/>
<dsNormal></dsNormal><br/>
<Data Type>reg</Data Type><Normal Text> du_flush_pipe_r</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text> dbg_stall_i_r</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Keyword>assign</Keyword><Normal Text> du_flush_pipe </Normal Text><Symbol>=</Symbol><Normal Text> du_flush_pipe_r</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Register du_flush_pipe</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		du_flush_pipe_r   </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		du_flush_pipe_r   </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>(</Symbol><Normal Text>dbg_stall_i_r </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dbg_stall_i </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text>du_except_stop</Normal Text><Symbol>);</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>end</Keyword><br/>
<Keyword>end</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Detect dbg_stall falling edge</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		dbg_stall_i_r   </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		dbg_stall_i_r   </Normal Text><Symbol><=</Symbol><Normal Text>  dbg_stall_i</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>end</Keyword><br/>
<Keyword>end</Keyword><br/>
<dsNormal></dsNormal><br/>
<Data Type>reg</Data Type><Normal Text>				dbg_ack</Normal Text><Symbol>;</Symbol><br/>
<Comment>//</Comment><br/>
<Comment>// Generate acknowledge -- just delay stb signal</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		dbg_ack   </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		dbg_ack_o </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>end</Keyword><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		dbg_ack   </Normal Text><Symbol><=</Symbol><Normal Text>  dbg_stb_i</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// valid when du_dat_i </Comment><br/>
<Normal Text>		dbg_ack_o </Normal Text><Symbol><=</Symbol><Normal Text>  dbg_ack </Normal Text><Symbol>&</Symbol><Normal Text> dbg_stb_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// valid when dbg_dat_o </Comment><br/>
<Normal Text>	</Normal Text><Keyword>end</Keyword><br/>
<Keyword>end</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>// </Comment><br/>
<Comment>// Register data output</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>    dbg_dat_o </Normal Text><Symbol><=</Symbol><Normal Text>  du_dat_i</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Preprocessor>`ifdef OR1200_DU_IMPLEMENTED</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Mode Register 1</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DMR1</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>24</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dmr1</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// DMR1 implemented</Comment><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>24</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dmr1</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// DMR1 not implemented</Comment><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> du_dmr1 </Normal Text><Symbol>=</Symbol><Normal Text> dmr1</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Mode Register 2</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DMR2</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>23</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dmr2</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// DMR2 implemented</Comment><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>23</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dmr2</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// DMR2 not implemented</Comment><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Stop Register</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DSR</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>	dsr</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// DSR implemented</Comment><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>	dsr</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// DSR not implemented</Comment><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Reason Register</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DRR</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>13</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			drr</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// DRR implemented</Comment><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>13</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			drr</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// DRR not implemented</Comment><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Value Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR0</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr0</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr0</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Value Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR1</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr1</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr1</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Value Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR2</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr2</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr2</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Value Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR3</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr3</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr3</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Value Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR4</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr4</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr4</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Value Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR5</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr5</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr5</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Value Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR6</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr6</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr6</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Value Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR7</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr7</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dvr7</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Control Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR0</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr0</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr0</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Control Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR1</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr1</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr1</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Control Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR2</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr2</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr2</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Control Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR3</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr3</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr3</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Control Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR4</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr4</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr4</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Control Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR5</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr5</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr5</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Control Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR6</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr6</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr6</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Control Register N</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR7</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr7</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dcr7</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Watchpoint Counter Register 0</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DWCR0</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dwcr0</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dwcr0</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Debug Watchpoint Counter Register 1</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DWCR1</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dwcr1</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			dwcr1</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Internal wires</Comment><br/>
<Comment>//</Comment><br/>
<Data Type>wire</Data Type><Normal Text>				dmr1_sel</Normal Text><Symbol>;</Symbol><Normal Text> 	</Normal Text><Comment>// DMR1 select</Comment><br/>
<Data Type>wire</Data Type><Normal Text>				dmr2_sel</Normal Text><Symbol>;</Symbol><Normal Text> 	</Normal Text><Comment>// DMR2 select</Comment><br/>
<Data Type>wire</Data Type><Normal Text>				dsr_sel</Normal Text><Symbol>;</Symbol><Normal Text> 	</Normal Text><Comment>// DSR select</Comment><br/>
<Data Type>wire</Data Type><Normal Text>				drr_sel</Normal Text><Symbol>;</Symbol><Normal Text> 	</Normal Text><Comment>// DRR select</Comment><br/>
<Data Type>wire</Data Type><Normal Text>				dvr0_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dvr1_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dvr2_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dvr3_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dvr4_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dvr5_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dvr6_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dvr7_sel</Normal Text><Symbol>;</Symbol><Normal Text> 	</Normal Text><Comment>// DVR selects</Comment><br/>
<Data Type>wire</Data Type><Normal Text>				dcr0_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dcr1_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dcr2_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dcr3_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dcr4_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dcr5_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dcr6_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dcr7_sel</Normal Text><Symbol>;</Symbol><Normal Text> 	</Normal Text><Comment>// DCR selects</Comment><br/>
<Data Type>wire</Data Type><Normal Text>				dwcr0_sel</Normal Text><Symbol>,</Symbol><br/>
<Normal Text>				dwcr1_sel</Normal Text><Symbol>;</Symbol><Normal Text> 	</Normal Text><Comment>// DWCR selects</Comment><br/>
<Data Type>reg</Data Type><Normal Text>				dbg_bp_r</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text> 				ex_freeze_q</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`ifdef OR1200_DU_HWBKPTS</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			match_cond0_ct</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			match_cond1_ct</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			match_cond2_ct</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			match_cond3_ct</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			match_cond4_ct</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			match_cond5_ct</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			match_cond6_ct</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			match_cond7_ct</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match_cond0_stb</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match_cond1_stb</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match_cond2_stb</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match_cond3_stb</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match_cond4_stb</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match_cond5_stb</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match_cond6_stb</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match_cond7_stb</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match0</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match1</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match2</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match3</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match4</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match5</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match6</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				match7</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				wpcntr0_match</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				wpcntr1_match</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				incr_wpcntr0</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				incr_wpcntr1</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			wp</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>				du_hwbkpt</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>				du_hwbkpt_hold</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`ifdef OR1200_DU_READREGS</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			spr_dat_o</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>13</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			except_stop</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// Exceptions that stop because of DSR</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_TB_IMPLEMENTED</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>				tb_enw</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			tb_wadr</Normal Text><Symbol>;</Symbol><br/>
<Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			tb_timstmp</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			tbia_dat_o</Normal Text><Symbol>;</Symbol><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			tbim_dat_o</Normal Text><Symbol>;</Symbol><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			tbar_dat_o</Normal Text><Symbol>;</Symbol><br/>
<Data Type>wire</Data Type><Normal Text>	</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text>			tbts_dat_o</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// DU registers address decoder</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DMR1</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dmr1_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DMR1</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DMR2</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dmr2_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DMR2</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DSR</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dsr_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DSR</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DRR</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> drr_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DRR</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR0</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr0_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR0</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR1</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr1_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR1</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR2</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr2_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR2</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR3</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr3_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR3</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR4</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr4_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR4</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR5</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr5_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR5</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR6</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr6_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR6</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR7</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr7_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR7</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR0</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr0_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR0</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR1</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr1_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR1</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR2</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr2_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR2</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR3</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr3_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR3</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR4</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr4_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR4</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR5</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr5_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR5</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR6</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr6_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR6</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR7</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr7_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR7</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DWCR0</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dwcr0_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DWCR0</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DWCR1</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dwcr1_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DWCR1</Preprocessor><Symbol>));</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>// Track previous ex_freeze to detect when signals are updated</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>  ex_freeze_q </Normal Text><Symbol><=</Symbol><Normal Text> ex_freeze</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Decode started exception</Comment><br/>
<Comment>//</Comment><br/>
<Comment>// du_except_stop comes from or1200_except</Comment><br/>
<Comment>//   </Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>du_except_stop </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> ex_freeze_q</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>	except_stop </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>14'b00_0000_0000_0000</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>casez</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>du_except_stop</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	        </Normal Text><Binary>14'b1</Binary><Symbol>?</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_TTE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>14'b01_</Binary><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_IE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Keyword>end</Keyword><br/>
<Normal Text>		</Normal Text><Binary>14'b00_1</Binary><Symbol>???</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_IME</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Keyword>end</Keyword><br/>
<Normal Text>		</Normal Text><Binary>14'b00_01</Binary><Symbol>??</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_IPFE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>14'b00_001</Binary><Symbol>?</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_BUSEE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Keyword>end</Keyword><br/>
<Normal Text>		</Normal Text><Binary>14'b00_0001_</Binary><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_IIE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>14'b00_0000_1</Binary><Symbol>???</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_AE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Keyword>end</Keyword><br/>
<Normal Text>		</Normal Text><Binary>14'b00_0000_01</Binary><Symbol>??</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_DME</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Keyword>end</Keyword><br/>
<Normal Text>		</Normal Text><Binary>14'b00_0000_001</Binary><Symbol>?</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_DPFE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>14'b00_0000_0001_</Binary><Symbol>????:</Symbol><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_BUSEE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>14'b00_0000_0000_1</Binary><Symbol>???:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_RE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Keyword>end</Keyword><br/>
<Normal Text>		</Normal Text><Binary>14'b00_0000_0000_01</Binary><Symbol>??:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_TE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>ex_freeze_q</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Keyword>end</Keyword><br/>
<Normal Text>		</Normal Text><Binary>14'b00_0000_0000_001</Binary><Symbol>?:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>		        except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_FPE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Keyword>end</Keyword><Normal Text>	  </Normal Text><br/>
<Normal Text>		</Normal Text><Binary>14'b00_0000_0000_0001</Binary><Symbol>:</Symbol><br/>
<Normal Text>			except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_SCE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>ex_freeze_q</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><br/>
<Normal Text>			except_stop </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>14'b00_0000_0000_0000</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><Normal Text> </Normal Text><Comment>// casez (du_except_stop)</Comment><br/>
<Keyword>end</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// dbg_bp_o is registered</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>assign</Keyword><Normal Text> dbg_bp_o </Normal Text><Symbol>=</Symbol><Normal Text> dbg_bp_r</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Breakpoint activation register</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dbg_bp_r </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>ex_freeze</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dbg_bp_r </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>|</Symbol><Normal Text>except_stop</Normal Text><br/>
<Preprocessor>`ifdef OR1200_DU_DMR1_ST</Preprocessor><br/>
<Normal Text>                        </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><Symbol>~((</Symbol><Normal Text>ex_insn</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>26</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_OR32_NOP</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> ex_insn</Normal Text><Symbol>[</Symbol><Integer>16</Integer><Symbol>])</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_ST</Preprocessor><Symbol>]</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DMR1_BT</Preprocessor><br/>
<Normal Text>                        </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>branch_op </Normal Text><Symbol>!=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_BRANCHOP_NOP</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>branch_op </Normal Text><Symbol>!=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_BRANCHOP_RFE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_BT</Preprocessor><Symbol>]</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Normal Text>			</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>        </Normal Text><Keyword>else</Keyword><br/>
<Normal Text>                dbg_bp_r </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>|</Symbol><Normal Text>except_stop</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DMR1</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DMR1</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dmr1 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>25'h000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Preprocessor>`ifdef OR1200_DU_HWBKPTS</Preprocessor><br/>
<Normal Text>		dmr1 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>24</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Normal Text>		dmr1 </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>,</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>23</Integer><Symbol>:</Symbol><Integer>22</Integer><Symbol>],</Symbol><Normal Text> </Normal Text><Hex>22'h00_0000</Hex><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dmr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>25'h000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DMR2</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DMR2</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dmr2 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>24'h00_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr2_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dmr2 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>23</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dmr2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>24'h00_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DSR</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DSR</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dsr </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>}};</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dsr_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dsr </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dsr </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>}};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DRR</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DRR</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		drr </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>14'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>drr_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		drr </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>13</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><br/>
<Normal Text>		drr </Normal Text><Symbol><=</Symbol><Normal Text>  drr </Normal Text><Symbol>|</Symbol><Normal Text> except_stop</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> drr </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>14'b0</Binary><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DVR0</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR0</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dvr0 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr0_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dvr0 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DVR1</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR1</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dvr1 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr1_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dvr1 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DVR2</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR2</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dvr2 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr2_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dvr2 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DVR3</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR3</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dvr3 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr3_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dvr3 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DVR4</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR4</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dvr4 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr4_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dvr4 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DVR5</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR5</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dvr5 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr5_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dvr5 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DVR6</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR6</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dvr6 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr6_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dvr6 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DVR7</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR7</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dvr7 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr7_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dvr7 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dvr7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DCR0</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR0</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dcr0 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr0_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dcr0 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DCR1</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR1</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dcr1 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr1_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dcr1 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DCR2</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR2</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dcr2 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr2_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dcr2 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DCR3</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR3</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dcr3 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr3_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dcr3 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DCR4</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR4</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dcr4 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr4_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dcr4 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DCR5</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR5</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dcr5 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr5_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dcr5 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DCR6</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR6</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dcr6 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr6_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dcr6 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DCR7</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DCR7</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dcr7 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr7_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dcr7 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dcr7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DWCR0</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DWCR0</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dwcr0 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dwcr0_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dwcr0 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>incr_wpcntr0</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dwcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><Normal Text>  dwcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>+</Symbol><Normal Text> </Normal Text><Hex>16'h0001</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dwcr0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Write to DWCR1</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DWCR1</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		dwcr1 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dwcr1_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dwcr1 </Normal Text><Symbol><=</Symbol><Normal Text>  spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>incr_wpcntr1</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		dwcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><Normal Text>  dwcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>+</Symbol><Normal Text> </Normal Text><Hex>16'h0001</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> dwcr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Read DU registers</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_READREGS</Preprocessor><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>spr_addr </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dsr </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> drr </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dmr2</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr4</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr7</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr4</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr7</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dwcr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dwcr1</Normal Text><br/>
<Preprocessor>`ifdef OR1200_DU_TB_IMPLEMENTED</Preprocessor><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> tb_wadr </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> tbia_dat_o </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> tbim_dat_o</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> tbar_dat_o </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> tbts_dat_o</Normal Text><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Normal Text>	</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>casez</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_DVR0</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DVR0</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr0</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR1</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DVR1</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr1</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR2</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DVR2</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr2</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR3</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DVR3</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr3</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR4</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DVR4</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr4</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR5</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DVR5</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr5</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR6</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DVR6</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr6</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DVR7</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DVR7</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr7</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR0</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DCR0</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr0</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR1</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DCR1</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr1</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR2</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DCR2</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr2</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR3</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DCR3</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr3</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR4</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DCR4</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr4</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR5</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DCR5</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr5</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR6</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DCR6</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr6</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DCR7</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DCR7</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr7</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DMR1</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DMR1</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>7'h00</Hex><Symbol>,</Symbol><Normal Text> dmr1</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DMR2</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DMR2</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>8'h00</Hex><Symbol>,</Symbol><Normal Text> dmr2</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DWCR0</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DWCR0</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dwcr0</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DWCR1</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DWCR1</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dwcr1</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DSR</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DSR</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Binary>18'b0</Binary><Symbol>,</Symbol><Normal Text> dsr</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_DRR</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_DRR</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Binary>18'b0</Binary><Symbol>,</Symbol><Normal Text> drr</Normal Text><Symbol>};</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`ifdef OR1200_DU_TB_IMPLEMENTED</Preprocessor><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_TBADR</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h000000</Hex><Symbol>,</Symbol><Normal Text> tb_wadr</Normal Text><Symbol>};</Symbol><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_TBIA</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> tbia_dat_o</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_TBIM</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> tbim_dat_o</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_TBAR</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> tbar_dat_o</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Preprocessor>`OR1200_DU_TBTS</Preprocessor><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> tbts_dat_o</Normal Text><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><br/>
<Normal Text>			spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// DSR alias</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>assign</Keyword><Normal Text> du_dsr </Normal Text><Symbol>=</Symbol><Normal Text> dsr</Normal Text><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Preprocessor>`ifdef OR1200_DU_HWBKPTS</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Compare To What (Match Condition 0)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text>		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text>	match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text>	match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text>	match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text>	match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text>	match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load/store EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// When To Compare (Match Condition 0)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> 		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text>	match_cond0_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>//comparison disabled</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond0_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond0_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Match Condition 0</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond0_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond0_ct</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond0_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 0</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match0</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW0</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match0</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match0</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match0</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Compare To What (Match Condition 1)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text>		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text>	match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text>	match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text>	match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text>	match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text>	match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load/store EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// When To Compare (Match Condition 1)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> 		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text>	match_cond1_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>//comparison disabled</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond1_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond1_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Match Condition 1</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond1_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond1_ct</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond1_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 1</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW1</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match1</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match1 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match1 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Compare To What (Match Condition 2)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text>		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text>	match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text>	match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text>	match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text>	match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text>	match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load/store EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// When To Compare (Match Condition 2)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> 		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text>	match_cond2_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>//comparison disabled</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond2_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond2_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Match Condition 2</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond2_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond2_ct</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond2_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 2</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW2</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match2</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match2 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match2 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Compare To What (Match Condition 3)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text>		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text>	match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text>	match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text>	match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text>	match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text>	match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load/store EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// When To Compare (Match Condition 3)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> 		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text>	match_cond3_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>//comparison disabled</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond3_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond3_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Match Condition 3</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond3_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond3_ct</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond3_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 3</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW3</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match3</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match3 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match3 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Compare To What (Match Condition 4)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr4 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text>		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text>	match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text>	match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text>	match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text>	match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text>	match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load/store EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// When To Compare (Match Condition 4)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr4 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> 		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text>	match_cond4_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>//comparison disabled</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond4_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond4_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Match Condition 4</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond4_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr4 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr4 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond4_ct</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond4_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 4</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match4 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW4</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match4</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match4 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match4 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Compare To What (Match Condition 5)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text>		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text>	match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text>	match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text>	match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text>	match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text>	match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load/store EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// When To Compare (Match Condition 5)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> 		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text>	match_cond5_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>//comparison disabled</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond5_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond5_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Match Condition 5</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond5_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond5_ct</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond5_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 5</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW5</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match5</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match5 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match5 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Compare To What (Match Condition 6)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text>		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text>	match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text>	match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text>	match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text>	match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text>	match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load/store EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// When To Compare (Match Condition 6)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> 		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text>	match_cond6_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>//comparison disabled</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond6_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond6_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Match Condition 6</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond6_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond6_ct</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond6_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 6</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW6</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match6</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match6 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match6 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Compare To What (Match Condition 7)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr7 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
<Normal Text>	</Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text>		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text>	match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text>	match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store EA</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text>	match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text>	match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// store data</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text>	match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text>	</Normal Text><Comment>// load/store EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// When To Compare (Match Condition 7)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr7 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> 		</Normal Text><Comment>// synopsys parallel_case</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text>	match_cond7_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>//comparison disabled</Comment><br/>
<Normal Text>		</Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text>	match_cond7_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text>		</Normal Text><Comment>// insn fetch EA</Comment><br/>
<Normal Text>		</Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond7_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Match Condition 7</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond7_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr7 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr7 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond7_ct</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond7_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>		</Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
<Normal Text>			</Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
<Normal Text>			 </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 7</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match7 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW7</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match7</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match7 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match7 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Increment Watchpoint Counter 0</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>wp </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dmr2</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR2_WCE0</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		incr_wpcntr0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>|(</Symbol><Normal Text>wp </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>dmr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR2_AWTC</Preprocessor><Symbol>]);</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><br/>
<Normal Text>		incr_wpcntr0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Match Condition Watchpoint Counter 0</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dwcr0</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dwcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_MATCH</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> dwcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		wpcntr0_match </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><br/>
<Normal Text>		wpcntr0_match </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 8</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wpcntr0_match </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW8</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr0_match</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr0_match </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr0_match </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Increment Watchpoint Counter 1</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>wp </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dmr2</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR2_WCE1</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		incr_wpcntr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>|(</Symbol><Normal Text>wp </Normal Text><Symbol>&</Symbol><Normal Text> dmr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR2_AWTC</Preprocessor><Symbol>]);</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><br/>
<Normal Text>		incr_wpcntr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Match Condition Watchpoint Counter 1</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dwcr1</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dwcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_MATCH</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> dwcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		wpcntr1_match </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><br/>
<Normal Text>		wpcntr1_match </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 9</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wpcntr1_match </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW9</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr1_match</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr1_match </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr1_match </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoint 10</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dbg_ewt_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW10</Preprocessor><Symbol>])</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> dbg_ewt_i</Normal Text><Symbol>;</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> dbg_ewt_i </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> dbg_ewt_i </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>];</Symbol><br/>
<Normal Text>		</Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>endcase</Keyword><br/>
<dsNormal></dsNormal><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Watchpoints can cause trap exception</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_HWBKPTS</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> du_hwbkpt </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>|(</Symbol><Normal Text>wp </Normal Text><Symbol>&</Symbol><Normal Text> dmr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR2_WGB</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text> du_hwbkpt_hold </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dbg_bp_r </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>dsr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DSR_TE</Preprocessor><Symbol>]);</Symbol><br/>
<Preprocessor>`else</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> du_hwbkpt </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Comment>// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception </Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		du_hwbkpt_hold </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>du_hwbkpt </Normal Text><Symbol>&</Symbol><Normal Text> ex_freeze</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		du_hwbkpt_hold </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>ex_freeze</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		du_hwbkpt_hold </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Preprocessor>`ifdef OR1200_DU_TB_IMPLEMENTED</Preprocessor><br/>
<Comment>//</Comment><br/>
<Comment>// Simple trace buffer</Comment><br/>
<Comment>// (right now hardcoded for Xilinx Virtex FPGAs)</Comment><br/>
<Comment>//</Comment><br/>
<Comment>// Stores last 256 instruction addresses, instruction</Comment><br/>
<Comment>// machine words and ALU results</Comment><br/>
<Comment>//</Comment><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Trace buffer write enable</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>assign</Keyword><Normal Text> tb_enw </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>ex_freeze </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~((</Symbol><Normal Text>ex_insn</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>26</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_OR32_NOP</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> ex_insn</Normal Text><Symbol>[</Symbol><Integer>16</Integer><Symbol>]);</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Trace buffer write address pointer</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		tb_wadr </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>tb_enw</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		tb_wadr </Normal Text><Symbol><=</Symbol><Normal Text>  tb_wadr </Normal Text><Symbol>+</Symbol><Normal Text> </Normal Text><Decimal>8'd1</Decimal><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Free running counter (time stamp)</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
<Normal Text>		tb_timstmp </Normal Text><Symbol><=</Symbol><Normal Text>  </Normal Text><Hex>32'h00000000</Hex><Symbol>;</Symbol><br/>
<Normal Text>	</Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>dbg_bp_r</Normal Text><Symbol>)</Symbol><br/>
<Normal Text>		tb_timstmp </Normal Text><Symbol><=</Symbol><Normal Text>  tb_timstmp </Normal Text><Symbol>+</Symbol><Normal Text> </Normal Text><Decimal>32'd1</Decimal><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Trace buffer RAMs</Comment><br/>
<Comment>//</Comment><br/>
<dsNormal></dsNormal><br/>
<Normal Text>or1200_dpram_256x32 tbia_ram</Normal Text><Symbol>(</Symbol><br/>
<Normal Text>	.clk_a</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.rst_a</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.addr_a</Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]),</Symbol><br/>
<Normal Text>	.ce_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.oe_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.do_a</Normal Text><Symbol>(</Symbol><Normal Text>tbia_dat_o</Normal Text><Symbol>),</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>	.clk_b</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.rst_b</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.addr_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_wadr</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.di_b</Normal Text><Symbol>(</Symbol><Normal Text>spr_dat_npc</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.ce_b</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.we_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_enw</Normal Text><Symbol>)</Symbol><br/>
<dsNormal></dsNormal><br/>
<Symbol>);</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>or1200_dpram_256x32 tbim_ram</Normal Text><Symbol>(</Symbol><br/>
<Normal Text>	.clk_a</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.rst_a</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.addr_a</Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]),</Symbol><br/>
<Normal Text>	.ce_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.oe_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.do_a</Normal Text><Symbol>(</Symbol><Normal Text>tbim_dat_o</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	</Normal Text><br/>
<Normal Text>	.clk_b</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.rst_b</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.addr_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_wadr</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.di_b</Normal Text><Symbol>(</Symbol><Normal Text>ex_insn</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.ce_b</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.we_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_enw</Normal Text><Symbol>)</Symbol><br/>
<Symbol>);</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>or1200_dpram_256x32 tbar_ram</Normal Text><Symbol>(</Symbol><br/>
<Normal Text>	.clk_a</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.rst_a</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.addr_a</Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]),</Symbol><br/>
<Normal Text>	.ce_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.oe_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.do_a</Normal Text><Symbol>(</Symbol><Normal Text>tbar_dat_o</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	</Normal Text><br/>
<Normal Text>	.clk_b</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.rst_b</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.addr_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_wadr</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.di_b</Normal Text><Symbol>(</Symbol><Normal Text>rf_dataw</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.ce_b</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.we_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_enw</Normal Text><Symbol>)</Symbol><br/>
<Symbol>);</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>or1200_dpram_256x32 tbts_ram</Normal Text><Symbol>(</Symbol><br/>
<Normal Text>	.clk_a</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.rst_a</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.addr_a</Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]),</Symbol><br/>
<Normal Text>	.ce_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.oe_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.do_a</Normal Text><Symbol>(</Symbol><Normal Text>tbts_dat_o</Normal Text><Symbol>),</Symbol><br/>
<dsNormal></dsNormal><br/>
<Normal Text>	.clk_b</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.rst_b</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.addr_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_wadr</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.di_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_timstmp</Normal Text><Symbol>),</Symbol><br/>
<Normal Text>	.ce_b</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
<Normal Text>	.we_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_enw</Normal Text><Symbol>)</Symbol><br/>
<Symbol>);</Symbol><br/>
<dsNormal></dsNormal><br/>
<Preprocessor>`else</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Keyword>assign</Keyword><Normal Text> tbia_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> tbim_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> tbar_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> tbts_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Preprocessor>`endif	</Preprocessor><Comment>// OR1200_DU_TB_IMPLEMENTED</Comment><br/>
<dsNormal></dsNormal><br/>
<Preprocessor>`else	</Preprocessor><Comment>// OR1200_DU_IMPLEMENTED</Comment><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// When DU is not implemented, drive all outputs as would when DU is disabled</Comment><br/>
<Comment>//</Comment><br/>
<Keyword>assign</Keyword><Normal Text> dbg_bp_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> du_dsr </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>}};</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> du_dmr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Integer>25</Integer><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>}};</Symbol><br/>
<Keyword>assign</Keyword><Normal Text> du_hwbkpt </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
<dsNormal></dsNormal><br/>
<Comment>//</Comment><br/>
<Comment>// Read DU registers</Comment><br/>
<Comment>//</Comment><br/>
<Preprocessor>`ifdef OR1200_DU_READREGS</Preprocessor><br/>
<Keyword>assign</Keyword><Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
<Preprocessor>`ifdef OR1200_DU_UNUSED_ZERO</Preprocessor><br/>
<Preprocessor>`endif</Preprocessor><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Preprocessor>`endif</Preprocessor><br/>
<dsNormal></dsNormal><br/>
<Keyword>endmodule</Keyword><br/>
